mirror of
https://github.com/embassy-rs/embassy.git
synced 2024-11-25 16:23:10 +00:00
Preliminary DMA support for RP2040
This commit is contained in:
Mathias
parent
0f74f870b0
commit
d35a1c9790
@ -1,39 +1,71 @@
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use core::pin::Pin;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::{Context, Poll};
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use embassy_hal_common::impl_peripheral;
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use embassy_hal_common::{impl_peripheral, into_ref, Peripheral, PeripheralRef};
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use futures::Future;
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use crate::pac::dma::vals;
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use crate::{pac, peripherals};
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pub struct Dma<T: Channel> {
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_inner: T,
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pub fn copy<'a, C: Channel, W: Word>(ch: impl Peripheral<P = C> + 'a, from: &[W], to: &mut [W]) -> Transfer<'a, C> {
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assert!(from.len() == to.len());
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into_ref!(ch);
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unsafe {
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let p = ch.regs();
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p.read_addr().write_value(from.as_ptr() as u32);
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p.write_addr().write_value(to.as_mut_ptr() as u32);
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p.trans_count().write_value(from.len() as u32);
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compiler_fence(Ordering::SeqCst);
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p.ctrl_trig().write(|w| {
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w.set_data_size(W::size());
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w.set_incr_read(true);
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w.set_incr_write(true);
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w.set_chain_to(ch.number());
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w.set_en(true);
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});
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// FIXME:
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while p.ctrl_trig().read().busy() {}
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compiler_fence(Ordering::SeqCst);
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}
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Transfer::new(ch)
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}
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impl<T: Channel> Dma<T> {
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pub fn copy(inner: T, from: &[u32], to: &mut [u32]) {
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assert!(from.len() == to.len());
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pub(crate) struct Transfer<'a, C: Channel> {
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channel: PeripheralRef<'a, C>,
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}
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unsafe {
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let p = inner.regs();
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impl<'a, C: Channel> Transfer<'a, C> {
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pub(crate) fn new(channel: impl Peripheral<P = C> + 'a) -> Self {
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into_ref!(channel);
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Self { channel }
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}
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}
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p.read_addr().write_value(from.as_ptr() as u32);
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p.write_addr().write_value(to.as_mut_ptr() as u32);
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p.trans_count().write_value(from.len() as u32);
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impl<'a, C: Channel> Drop for Transfer<'a, C> {
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fn drop(&mut self) {
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// self.channel.request_stop();
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// while self.channel.is_running() {}
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}
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}
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compiler_fence(Ordering::SeqCst);
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p.ctrl_trig().write(|w| {
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w.set_data_size(vals::DataSize::SIZE_WORD);
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w.set_incr_read(true);
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w.set_incr_write(true);
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w.set_chain_to(inner.number());
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w.set_en(true);
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});
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while p.ctrl_trig().read().busy() {}
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compiler_fence(Ordering::SeqCst);
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}
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impl<'a, C: Channel> Unpin for Transfer<'a, C> {}
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impl<'a, C: Channel> Future for Transfer<'a, C> {
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type Output = ();
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fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
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// self.channel.set_waker(cx.waker());
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// if self.channel.is_running() {
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// Poll::Pending
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// } else {
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Poll::Ready(())
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// }
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}
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}
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@ -42,38 +74,77 @@ pub struct NoDma;
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impl_peripheral!(NoDma);
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mod sealed {
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use super::*;
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pub trait Channel {}
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pub trait Channel {
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fn number(&self) -> u8;
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pub trait Word {}
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}
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fn regs(&self) -> pac::dma::Channel {
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pac::DMA.ch(self.number() as _)
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pub trait Channel: Peripheral<P = Self> + sealed::Channel + Into<AnyChannel> + Sized + 'static {
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fn number(&self) -> u8;
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fn regs(&self) -> pac::dma::Channel {
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pac::DMA.ch(self.number() as _)
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}
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fn degrade(self) -> AnyChannel {
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AnyChannel {
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number: self.number(),
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}
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}
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}
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pub trait Channel: sealed::Channel {}
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pub trait Word: sealed::Word {
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fn size() -> vals::DataSize;
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}
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impl sealed::Word for u8 {}
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impl Word for u8 {
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fn size() -> vals::DataSize {
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vals::DataSize::SIZE_BYTE
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}
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}
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impl sealed::Word for u16 {}
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impl Word for u16 {
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fn size() -> vals::DataSize {
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vals::DataSize::SIZE_HALFWORD
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}
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}
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impl sealed::Word for u32 {}
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impl Word for u32 {
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fn size() -> vals::DataSize {
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vals::DataSize::SIZE_WORD
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}
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}
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pub struct AnyChannel {
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number: u8,
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}
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impl Channel for AnyChannel {}
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impl sealed::Channel for AnyChannel {
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impl_peripheral!(AnyChannel);
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impl sealed::Channel for AnyChannel {}
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impl Channel for AnyChannel {
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fn number(&self) -> u8 {
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self.number
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}
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}
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macro_rules! channel {
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($type:ident, $num:expr) => {
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impl Channel for peripherals::$type {}
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impl sealed::Channel for peripherals::$type {
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($name:ident, $num:expr) => {
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impl sealed::Channel for peripherals::$name {}
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impl Channel for peripherals::$name {
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fn number(&self) -> u8 {
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$num
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}
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}
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impl From<peripherals::$name> for crate::dma::AnyChannel {
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fn from(val: peripherals::$name) -> Self {
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crate::dma::Channel::degrade(val)
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}
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}
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};
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}
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@ -2,6 +2,7 @@ use core::marker::PhantomData;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use crate::dma::{AnyChannel, Channel};
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use crate::gpio::sealed::Pin;
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use crate::gpio::AnyPin;
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use crate::{pac, peripherals, Peripheral};
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@ -76,26 +77,27 @@ pub enum Error {
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Framing,
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}
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pub struct Uart<'d, T: Instance> {
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tx: UartTx<'d, T>,
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rx: UartRx<'d, T>,
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pub struct Uart<'d, T: Instance, M: Mode> {
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tx: UartTx<'d, T, M>,
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rx: UartRx<'d, T, M>,
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}
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pub struct UartTx<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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pub struct UartTx<'d, T: Instance, M: Mode> {
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tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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phantom: PhantomData<(&'d mut T, M)>,
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}
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pub struct UartRx<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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pub struct UartRx<'d, T: Instance, M: Mode> {
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rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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phantom: PhantomData<(&'d mut T, M)>,
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}
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impl<'d, T: Instance> UartTx<'d, T> {
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fn new() -> Self {
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Self { phantom: PhantomData }
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}
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pub async fn write(&mut self, _buffer: &[u8]) -> Result<(), Error> {
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todo!()
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impl<'d, T: Instance, M: Mode> UartTx<'d, T, M> {
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fn new(tx_dma: Option<PeripheralRef<'d, AnyChannel>>) -> Self {
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Self {
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tx_dma,
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phantom: PhantomData,
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}
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}
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pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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@ -116,13 +118,29 @@ impl<'d, T: Instance> UartTx<'d, T> {
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}
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}
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impl<'d, T: Instance> UartRx<'d, T> {
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fn new() -> Self {
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Self { phantom: PhantomData }
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impl<'d, T: Instance> UartTx<'d, T, Async> {
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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if let Some(ch) = &mut self.tx_dma {
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unsafe {
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T::regs().uartdmacr().modify(|reg| {
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reg.set_txdmae(true);
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});
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}
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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let transfer = crate::dma::copy(ch, buffer, unsafe { T::regs().uartdr().ptr() });
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transfer.await;
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}
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Ok(())
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}
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}
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pub async fn read(&mut self, _buffer: &mut [u8]) -> Result<(), Error> {
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todo!();
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impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
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fn new(rx_dma: Option<PeripheralRef<'d, AnyChannel>>) -> Self {
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Self {
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rx_dma,
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phantom: PhantomData,
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}
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}
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pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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@ -150,25 +168,42 @@ impl<'d, T: Instance> UartRx<'d, T> {
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}
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}
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impl<'d, T: Instance> Uart<'d, T> {
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impl<'d, T: Instance> UartRx<'d, T, Async> {
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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if let Some(ch) = &mut self.rx_dma {
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unsafe {
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T::regs().uartdmacr().modify(|reg| {
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reg.set_rxdmae(true);
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});
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}
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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let transfer = crate::dma::copy(ch, unsafe { T::regs().uartdr().ptr() }, buffer);
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transfer.await;
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> Uart<'d, T, Blocking> {
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/// Create a new UART without hardware flow control
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pub fn new(
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pub fn new_blocking(
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uart: impl Peripheral<P = T> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(tx, rx);
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Self::new_inner(uart, rx.map_into(), tx.map_into(), None, None, config)
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Self::new_inner(uart, rx.map_into(), tx.map_into(), None, None, None, None, config)
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}
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/// Create a new UART with hardware flow control (RTS/CTS)
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pub fn new_with_rtscts(
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pub fn new_with_rtscts_blocking(
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uart: impl Peripheral<P = T> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
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rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
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cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(tx, rx, cts, rts);
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@ -176,18 +211,72 @@ impl<'d, T: Instance> Uart<'d, T> {
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uart,
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rx.map_into(),
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tx.map_into(),
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Some(cts.map_into()),
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Some(rts.map_into()),
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Some(cts.map_into()),
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None,
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None,
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config,
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)
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}
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}
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impl<'d, T: Instance> Uart<'d, T, Async> {
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/// Create a new DMA enabled UART without hardware flow control
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pub fn new(
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uart: impl Peripheral<P = T> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx_dma: impl Peripheral<P = impl Channel> + 'd,
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rx_dma: impl Peripheral<P = impl Channel> + 'd,
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config: Config,
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) -> Self {
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into_ref!(tx, rx, tx_dma, rx_dma);
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Self::new_inner(
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uart,
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rx.map_into(),
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tx.map_into(),
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None,
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None,
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Some(tx_dma.map_into()),
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Some(rx_dma.map_into()),
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config,
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)
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}
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/// Create a new DMA enabled UART with hardware flow control (RTS/CTS)
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pub fn new_with_rtscts(
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uart: impl Peripheral<P = T> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
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cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
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tx_dma: impl Peripheral<P = impl Channel> + 'd,
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rx_dma: impl Peripheral<P = impl Channel> + 'd,
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config: Config,
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) -> Self {
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into_ref!(tx, rx, cts, rts, tx_dma, rx_dma);
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Self::new_inner(
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uart,
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rx.map_into(),
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tx.map_into(),
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Some(rts.map_into()),
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Some(cts.map_into()),
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Some(tx_dma.map_into()),
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Some(rx_dma.map_into()),
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config,
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)
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}
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}
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impl<'d, T: Instance, M: Mode> Uart<'d, T, M> {
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fn new_inner(
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_uart: impl Peripheral<P = T> + 'd,
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tx: PeripheralRef<'d, AnyPin>,
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rx: PeripheralRef<'d, AnyPin>,
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cts: Option<PeripheralRef<'d, AnyPin>>,
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rts: Option<PeripheralRef<'d, AnyPin>>,
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cts: Option<PeripheralRef<'d, AnyPin>>,
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tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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config: Config,
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) -> Self {
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into_ref!(_uart);
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@ -246,15 +335,13 @@ impl<'d, T: Instance> Uart<'d, T> {
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}
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Self {
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tx: UartTx::new(),
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rx: UartRx::new(),
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tx: UartTx::new(tx_dma),
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rx: UartRx::new(rx_dma),
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}
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}
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}
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.tx.write(buffer).await
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}
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impl<'d, T: Instance, M: Mode> Uart<'d, T, M> {
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pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.tx.blocking_write(buffer)
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}
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@ -263,26 +350,31 @@ impl<'d, T: Instance> Uart<'d, T> {
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self.tx.blocking_flush()
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}
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.rx.read(buffer).await
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}
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pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.rx.blocking_read(buffer)
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}
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/// Split the Uart into a transmitter and receiver, which is
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/// particuarly useful when having two tasks correlating to
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/// transmitting and receiving.
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pub fn split(self) -> (UartTx<'d, T>, UartRx<'d, T>) {
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/// Split the Uart into a transmitter and receiver, which is particuarly
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/// useful when having two tasks correlating to transmitting and receiving.
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pub fn split(self) -> (UartTx<'d, T, M>, UartRx<'d, T, M>) {
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(self.tx, self.rx)
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}
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}
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impl<'d, T: Instance> Uart<'d, T, Async> {
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.tx.write(buffer).await
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}
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.rx.read(buffer).await
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}
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}
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mod eh02 {
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use super::*;
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impl<'d, T: Instance> embedded_hal_02::serial::Read<u8> for UartRx<'d, T> {
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impl<'d, T: Instance, M: Mode> embedded_hal_02::serial::Read<u8> for UartRx<'d, T, M> {
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type Error = Error;
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fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
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let r = T::regs();
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@ -306,7 +398,7 @@ mod eh02 {
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}
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}
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impl<'d, T: Instance> embedded_hal_02::blocking::serial::Write<u8> for UartTx<'d, T> {
|
||||
impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for UartTx<'d, T, M> {
|
||||
type Error = Error;
|
||||
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
||||
self.blocking_write(buffer)
|
||||
@ -316,14 +408,14 @@ mod eh02 {
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> embedded_hal_02::serial::Read<u8> for Uart<'d, T> {
|
||||
impl<'d, T: Instance, M: Mode> embedded_hal_02::serial::Read<u8> for Uart<'d, T, M> {
|
||||
type Error = Error;
|
||||
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
|
||||
embedded_hal_02::serial::Read::read(&mut self.rx)
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> embedded_hal_02::blocking::serial::Write<u8> for Uart<'d, T> {
|
||||
impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for Uart<'d, T, M> {
|
||||
type Error = Error;
|
||||
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
||||
self.blocking_write(buffer)
|
||||
@ -419,6 +511,8 @@ cfg_if::cfg_if! {
|
||||
mod sealed {
|
||||
use super::*;
|
||||
|
||||
pub trait Mode {}
|
||||
|
||||
pub trait Instance {
|
||||
fn regs() -> pac::uart::Uart;
|
||||
}
|
||||
@ -428,6 +522,21 @@ mod sealed {
|
||||
pub trait RtsPin<T: Instance> {}
|
||||
}
|
||||
|
||||
pub trait Mode: sealed::Mode {}
|
||||
|
||||
macro_rules! impl_mode {
|
||||
($name:ident) => {
|
||||
impl sealed::Mode for $name {}
|
||||
impl Mode for $name {}
|
||||
};
|
||||
}
|
||||
|
||||
pub struct Blocking;
|
||||
pub struct Async;
|
||||
|
||||
impl_mode!(Blocking);
|
||||
impl_mode!(Async);
|
||||
|
||||
pub trait Instance: sealed::Instance {}
|
||||
|
||||
macro_rules! impl_instance {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user