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rp: wait until read matches for PSM accesses.
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@ -383,25 +383,29 @@ unsafe fn pre_init() {
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//
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// The PSM order is SIO -> PROC0 -> PROC1.
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// So, we have to force-on PROC0 to prevent it from getting reset when resetting SIO.
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pac::PSM.frce_on().write(|w| {
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pac::PSM.frce_on().write_and_wait(|w| {
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w.set_proc0(true);
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});
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// Then reset SIO and PROC1.
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pac::PSM.frce_off().write(|w| {
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pac::PSM.frce_off().write_and_wait(|w| {
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w.set_sio(true);
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w.set_proc1(true);
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});
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// clear force_off first, force_on second. The other way around would reset PROC0.
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pac::PSM.frce_off().write(|_| {});
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pac::PSM.frce_on().write(|_| {});
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pac::PSM.frce_off().write_and_wait(|_| {});
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pac::PSM.frce_on().write_and_wait(|_| {});
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}
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/// Extension trait for PAC regs, adding atomic xor/bitset/bitclear writes.
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#[allow(unused)]
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trait RegExt<T: Copy> {
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#[allow(unused)]
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fn write_xor<R>(&self, f: impl FnOnce(&mut T) -> R) -> R;
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fn write_set<R>(&self, f: impl FnOnce(&mut T) -> R) -> R;
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fn write_clear<R>(&self, f: impl FnOnce(&mut T) -> R) -> R;
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fn write_and_wait<R>(&self, f: impl FnOnce(&mut T) -> R) -> R
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where
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T: PartialEq;
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}
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impl<T: Default + Copy, A: pac::common::Write> RegExt<T> for pac::common::Reg<T, A> {
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@ -434,4 +438,17 @@ impl<T: Default + Copy, A: pac::common::Write> RegExt<T> for pac::common::Reg<T,
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}
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res
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}
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fn write_and_wait<R>(&self, f: impl FnOnce(&mut T) -> R) -> R
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where
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T: PartialEq,
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{
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let mut val = Default::default();
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let res = f(&mut val);
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unsafe {
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self.as_ptr().write_volatile(val);
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while self.as_ptr().read_volatile() != val {}
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}
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res
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}
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}
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