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Allow Uart::new_half_duplex for all usart_vx
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@ -933,7 +933,6 @@ impl<'d, T: BasicInstance> Uart<'d, T, Async> {
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/// I/O in idle or in reception.
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/// Apart from this, the communication protocol is similar to normal USART mode. Any conflict
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/// on the line must be managed by software (for instance by using a centralized arbiter).
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#[cfg(not(any(usart_v1, usart_v2)))]
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#[doc(alias("HDSEL"))]
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pub fn new_half_duplex(
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peri: impl Peripheral<P = T> + 'd,
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@ -943,7 +942,10 @@ impl<'d, T: BasicInstance> Uart<'d, T, Async> {
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rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
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mut config: Config,
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) -> Result<Self, ConfigError> {
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#[cfg(not(any(usart_v1, usart_v2)))]
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{
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config.swap_rx_tx = false;
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}
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config.half_duplex = true;
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Self::new_inner(
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@ -1084,14 +1086,16 @@ impl<'d, T: BasicInstance> Uart<'d, T, Blocking> {
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/// I/O in idle or in reception.
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/// Apart from this, the communication protocol is similar to normal USART mode. Any conflict
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/// on the line must be managed by software (for instance by using a centralized arbiter).
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#[cfg(not(any(usart_v1, usart_v2)))]
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#[doc(alias("HDSEL"))]
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pub fn new_blocking_half_duplex(
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peri: impl Peripheral<P = T> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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mut config: Config,
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) -> Result<Self, ConfigError> {
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#[cfg(not(any(usart_v1, usart_v2)))]
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{
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config.swap_rx_tx = false;
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}
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config.half_duplex = true;
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Self::new_inner(
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@ -1354,10 +1358,9 @@ fn configure(
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}
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});
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#[cfg(not(usart_v1))]
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r.cr3().modify(|w| {
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#[cfg(not(usart_v1))]
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w.set_onebit(config.assume_noise_free);
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#[cfg(any(usart_v3, usart_v4))]
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w.set_hdsel(config.half_duplex);
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});
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