mirror of
https://github.com/embassy-rs/embassy.git
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stm32/rcc: port F0 to new API.
This commit is contained in:
Dario Nieuwenhuis
parent
b7c147445a
commit
ccd2c574c3
7
ci.sh
7
ci.sh
@ -88,6 +88,13 @@ cargo batch \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,exti \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f038f6,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030c6,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f058t8,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030r8,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f031k6,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030rc,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f070f6,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f078vb,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f042g4,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f072c8,defmt,exti,time-driver-any,time \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f401ve,defmt,exti,time-driver-any \
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@ -68,7 +68,7 @@ rand_core = "0.6.3"
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sdio-host = "0.5.0"
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critical-section = "1.1"
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#stm32-metapac = { version = "15" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8a3ad0b738292ae40af201d79b28db60fe876e11" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7734584b2007766b1c5a6a7f2654fdb442fa211a" }
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vcell = "0.1.3"
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bxcan = "0.7.0"
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nb = "1.0.0"
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@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
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proc-macro2 = "1.0.36"
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quote = "1.0.15"
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#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8a3ad0b738292ae40af201d79b28db60fe876e11", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7734584b2007766b1c5a6a7f2654fdb442fa211a", default-features = false, features = ["metadata"]}
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[features]
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@ -1,27 +1,64 @@
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use stm32_metapac::flash::vals::Latency;
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use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Sw, Usbsw};
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use crate::pac::flash::vals::Latency;
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use crate::pac::rcc::vals::Pllsrc;
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pub use crate::pac::rcc::vals::{
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Hpre as AHBPrescaler, Pllmul as PllMul, Ppre as APBPrescaler, Prediv as PllPreDiv, Sw as Sysclk,
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};
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use crate::pac::{FLASH, RCC};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(8_000_000);
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/// Configuration of the clocks
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum HseMode {
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/// crystal/ceramic oscillator (HSEBYP=0)
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Oscillator,
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/// external analog clock (low swing) (HSEBYP=1)
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Bypass,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub struct Hse {
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/// HSE frequency.
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pub freq: Hertz,
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/// HSE mode.
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pub mode: HseMode,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum PllSource {
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HSE,
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HSI,
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#[cfg(rcc_f0v4)]
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HSI48,
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}
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#[derive(Clone, Copy)]
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pub struct Pll {
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pub src: PllSource,
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/// PLL pre-divider.
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///
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/// hse takes precedence over hsi48 if both are enabled
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/// On some chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
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pub prediv: PllPreDiv,
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/// PLL multiplication factor.
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pub mul: PllMul,
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}
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/// Clocks configutation
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#[non_exhaustive]
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pub struct Config {
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pub hse: Option<Hertz>,
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pub bypass_hse: bool,
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pub usb_pll: bool,
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pub hsi: bool,
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pub hse: Option<Hse>,
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#[cfg(crs)]
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pub hsi48: Option<super::Hsi48Config>,
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pub sys: Sysclk,
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pub sys_ck: Option<Hertz>,
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pub hclk: Option<Hertz>,
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pub pclk: Option<Hertz>,
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pub pll: Option<Pll>,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub ls: super::LsConfig,
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}
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@ -29,168 +66,167 @@ pub struct Config {
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impl Default for Config {
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fn default() -> Self {
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Self {
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hse: Default::default(),
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bypass_hse: Default::default(),
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usb_pll: Default::default(),
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hsi: true,
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hse: None,
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#[cfg(crs)]
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hsi48: Some(Default::default()),
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sys_ck: Default::default(),
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hclk: Default::default(),
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pclk: Default::default(),
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sys: Sysclk::HSI,
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pll: None,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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ls: Default::default(),
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}
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}
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}
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/// Initialize and Set the clock frequencies
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pub(crate) unsafe fn init(config: Config) {
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let sysclk = config.sys_ck.map(|v| v.0).unwrap_or(HSI_FREQ.0);
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// Configure HSI
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let hsi = match config.hsi {
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false => {
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RCC.cr().modify(|w| w.set_hsion(false));
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None
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}
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true => {
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RCC.cr().modify(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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Some(HSI_FREQ)
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}
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};
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// Configure HSE
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let hse = match config.hse {
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None => {
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RCC.cr().modify(|w| w.set_hseon(false));
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None
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}
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Some(hse) => {
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match hse.mode {
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HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
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HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
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}
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RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
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RCC.cr().modify(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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Some(hse.freq)
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}
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};
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// configure HSI48
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#[cfg(crs)]
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let hsi48 = config.hsi48.map(|config| super::init_hsi48(config));
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#[cfg(not(crs))]
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let hsi48: Option<Hertz> = None;
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let (src_clk, use_hsi48) = config.hse.map(|v| (v.0, false)).unwrap_or_else(|| {
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if hsi48.is_some() {
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return (48_000_000, true);
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// Enable PLL
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let pll = config.pll.map(|pll| {
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let (src_val, src_freq) = match pll.src {
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#[cfg(not(any(rcc_f0v1, rcc_f0v2)))]
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PllSource::HSI => (Pllsrc::HSI_DIV_PREDIV, unwrap!(hsi)),
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#[cfg(any(rcc_f0v1, rcc_f0v2))]
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PllSource::HSI => {
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if pll.prediv != PllPreDiv::DIV2 {
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panic!("if PLL source is HSI, PLL prediv must be 2.");
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}
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(HSI_FREQ.0, false)
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});
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let (pllmul_bits, real_sysclk) = if sysclk == src_clk {
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(None, sysclk)
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} else {
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let prediv = if config.hse.is_some() { 1 } else { 2 };
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let pllmul = (2 * prediv * sysclk + src_clk) / src_clk / 2;
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let pllmul = pllmul.max(2).min(16);
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let pllmul_bits = pllmul as u8 - 2;
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let real_sysclk = pllmul * src_clk / prediv;
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(Some(pllmul_bits), real_sysclk)
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(Pllsrc::HSI_DIV2, unwrap!(hsi))
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}
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PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)),
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#[cfg(rcc_f0v4)]
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PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)),
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};
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let in_freq = src_freq / pll.prediv;
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assert!(max::PLL_IN.contains(&in_freq));
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let out_freq = in_freq * pll.mul;
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assert!(max::PLL_OUT.contains(&out_freq));
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let hpre_bits = config
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.hclk
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.map(|hclk| match real_sysclk / hclk.0 {
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0 => unreachable!(),
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1 => 0b0111,
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2 => 0b1000,
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3..=5 => 0b1001,
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6..=11 => 0b1010,
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12..=39 => 0b1011,
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40..=95 => 0b1100,
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96..=191 => 0b1101,
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192..=383 => 0b1110,
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_ => 0b1111,
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})
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.unwrap_or(0b0111);
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let hclk = real_sysclk / (1 << (hpre_bits - 0b0111));
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let ppre_bits = config
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.pclk
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.map(|pclk| match hclk / pclk.0 {
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0 => unreachable!(),
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1 => 0b011,
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2 => 0b100,
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3..=5 => 0b101,
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6..=11 => 0b110,
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_ => 0b111,
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})
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.unwrap_or(0b011);
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let ppre: u8 = 1 << (ppre_bits - 0b011);
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let pclk = hclk / u32::from(ppre);
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let timer_mul = if ppre == 1 { 1 } else { 2 };
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FLASH.acr().write(|w| {
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w.set_latency(if real_sysclk <= 24_000_000 {
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Latency::WS0
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} else {
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Latency::WS1
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RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv));
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RCC.cfgr().modify(|w| {
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w.set_pllmul(pll.mul);
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w.set_pllsrc(src_val);
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});
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});
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match (config.hse.is_some(), use_hsi48) {
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(true, _) => {
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RCC.cr().modify(|w| {
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w.set_csson(true);
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w.set_hseon(true);
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w.set_hsebyp(config.bypass_hse);
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});
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while !RCC.cr().read().hserdy() {}
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if pllmul_bits.is_some() {
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RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSE_DIV_PREDIV))
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}
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}
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// use_hsi48 will always be false for stm32f0x0
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#[cfg(not(stm32f0x0))]
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(false, true) => {
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RCC.cr2().modify(|w| w.set_hsi48on(true));
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while !RCC.cr2().read().hsi48rdy() {}
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if pllmul_bits.is_some() {
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RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSI48_DIV_PREDIV))
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}
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}
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_ => {
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RCC.cr().modify(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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if pllmul_bits.is_some() {
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RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSI_DIV2))
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}
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}
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}
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if config.usb_pll {
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RCC.cfgr3().modify(|w| w.set_usbsw(Usbsw::PLL1_P));
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}
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// TODO: Option to use CRS (Clock Recovery)
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if let Some(pllmul_bits) = pllmul_bits {
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RCC.cfgr().modify(|w| w.set_pllmul(Pllmul::from_bits(pllmul_bits)));
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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RCC.cfgr().modify(|w| {
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w.set_ppre(Ppre::from_bits(ppre_bits));
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w.set_hpre(Hpre::from_bits(hpre_bits));
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w.set_sw(Sw::PLL1_P)
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out_freq
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});
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} else {
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RCC.cfgr().modify(|w| {
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w.set_ppre(Ppre::from_bits(ppre_bits));
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w.set_hpre(Hpre::from_bits(hpre_bits));
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if config.hse.is_some() {
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w.set_sw(Sw::HSE);
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} else if use_hsi48 {
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#[cfg(not(stm32f0x0))]
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w.set_sw(Sw::HSI48);
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} else {
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w.set_sw(Sw::HSI)
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}
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})
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}
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// Configure sysclk
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let sys = match config.sys {
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Sysclk::HSI => unwrap!(hsi),
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Sysclk::HSE => unwrap!(hse),
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Sysclk::PLL1_P => unwrap!(pll),
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#[cfg(rcc_f0v4)]
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Sysclk::HSI48 => unwrap!(hsi48),
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#[allow(unreachable_patterns)]
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_ => unreachable!(),
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};
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let hclk = sys / config.ahb_pre;
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let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
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assert!(max::HCLK.contains(&hclk));
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assert!(max::PCLK1.contains(&pclk1));
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// Set latency based on HCLK frquency
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let latency = match hclk.0 {
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..=24_000_000 => Latency::WS0,
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_ => Latency::WS1,
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};
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FLASH.acr().modify(|w| {
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w.set_latency(latency);
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w.set_prftbe(true);
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});
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// Set prescalers
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// CFGR has been written before (PLL, PLL48) don't overwrite these settings
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RCC.cfgr().modify(|w| {
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w.set_ppre(config.apb1_pre);
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w.set_hpre(config.ahb_pre);
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});
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// Wait for the new prescalers to kick in
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// "The clocks are divided with the new prescaler factor from
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// 1 to 16 AHB cycles after write"
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cortex_m::asm::delay(16);
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// CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
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RCC.cfgr().modify(|w| w.set_sw(config.sys));
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while RCC.cfgr().read().sws() != config.sys {}
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let rtc = config.ls.init();
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set_clocks!(
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hsi: None,
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lse: None,
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sys: Some(Hertz(real_sysclk)),
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pclk1: Some(Hertz(pclk)),
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pclk2: Some(Hertz(pclk)),
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pclk1_tim: Some(Hertz(pclk * timer_mul)),
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pclk2_tim: Some(Hertz(pclk * timer_mul)),
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hclk1: Some(Hertz(hclk)),
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rtc: rtc,
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hsi: hsi,
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hse: hse,
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pll1_p: pll,
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sys: Some(sys),
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pclk1: Some(pclk1),
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pclk2: Some(pclk1),
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pclk1_tim: Some(pclk1_tim),
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pclk2_tim: Some(pclk1_tim),
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hclk1: Some(hclk),
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#[cfg(all(not(rcc_f37), adc3_common))]
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adc34: Some(adc34),
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#[cfg(stm32f334)]
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hrtim: hrtim,
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hsi48: hsi48,
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// TODO:
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pll1_p: None,
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rtc: rtc,
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lse: None,
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);
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}
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mod max {
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use core::ops::RangeInclusive;
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use crate::time::Hertz;
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|
||||
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(32_000_000);
|
||||
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(32_000_000);
|
||||
|
||||
pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
|
||||
pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
|
||||
|
||||
pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(24_000_000);
|
||||
pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(48_000_000);
|
||||
}
|
||||
|
||||
@ -4,7 +4,7 @@ use embassy_hal_internal::into_ref;
|
||||
|
||||
use crate::gpio::sealed::AFType;
|
||||
use crate::gpio::Speed;
|
||||
#[cfg(not(any(stm32f1, rcc_f3v1, rcc_f37)))]
|
||||
#[cfg(not(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37)))]
|
||||
pub use crate::pac::rcc::vals::Mcopre as McoPrescaler;
|
||||
#[cfg(not(any(rcc_f2, rcc_f410, rcc_f4, rcc_f7, rcc_h50, rcc_h5, rcc_h7ab, rcc_h7rm0433, rcc_h7)))]
|
||||
pub use crate::pac::rcc::vals::Mcosel as McoSource;
|
||||
@ -13,7 +13,7 @@ pub use crate::pac::rcc::vals::{Mco1sel as Mco1Source, Mco2sel as Mco2Source};
|
||||
use crate::pac::RCC;
|
||||
use crate::{peripherals, Peripheral};
|
||||
|
||||
#[cfg(any(stm32f1, rcc_f3v1, rcc_f37))]
|
||||
#[cfg(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37))]
|
||||
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
|
||||
pub enum McoPrescaler {
|
||||
DIV1,
|
||||
@ -43,7 +43,7 @@ macro_rules! impl_peri {
|
||||
|
||||
r.modify(|w| {
|
||||
w.$set_source(source);
|
||||
#[cfg(not(any(stm32f1, rcc_f3v1, rcc_f37)))]
|
||||
#[cfg(not(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37)))]
|
||||
w.$set_prescaler(_prescaler);
|
||||
});
|
||||
}
|
||||
|
||||
@ -18,17 +18,17 @@ mod hsi48;
|
||||
#[cfg(crs)]
|
||||
pub use hsi48::*;
|
||||
|
||||
#[cfg_attr(rcc_f0, path = "f0.rs")]
|
||||
#[cfg_attr(any(stm32f1), path = "f1.rs")]
|
||||
#[cfg_attr(any(stm32f3), path = "f3.rs")]
|
||||
#[cfg_attr(stm32f0, path = "f0.rs")]
|
||||
#[cfg_attr(stm32f1, path = "f1.rs")]
|
||||
#[cfg_attr(stm32f3, path = "f3.rs")]
|
||||
#[cfg_attr(any(stm32f2, stm32f4, stm32f7), path = "f.rs")]
|
||||
#[cfg_attr(rcc_c0, path = "c0.rs")]
|
||||
#[cfg_attr(rcc_g0, path = "g0.rs")]
|
||||
#[cfg_attr(rcc_g4, path = "g4.rs")]
|
||||
#[cfg_attr(stm32c0, path = "c0.rs")]
|
||||
#[cfg_attr(stm32g0, path = "g0.rs")]
|
||||
#[cfg_attr(stm32g4, path = "g4.rs")]
|
||||
#[cfg_attr(any(stm32h5, stm32h7), path = "h.rs")]
|
||||
#[cfg_attr(any(stm32l0, stm32l1, stm32l4, stm32l5, stm32wb, stm32wl), path = "l.rs")]
|
||||
#[cfg_attr(rcc_u5, path = "u5.rs")]
|
||||
#[cfg_attr(rcc_wba, path = "wba.rs")]
|
||||
#[cfg_attr(stm32u5, path = "u5.rs")]
|
||||
#[cfg_attr(stm32wba, path = "wba.rs")]
|
||||
mod _version;
|
||||
|
||||
pub use _version::*;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user