stm32/rcc: port F0 to new API.

ci.sh

@@ -88,6 +88,13 @@ cargo batch  \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,exti \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f038f6,defmt,exti,time-driver-any,time \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030c6,defmt,exti,time-driver-any,time \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f058t8,defmt,exti,time-driver-any,time \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030r8,defmt,exti,time-driver-any,time \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f031k6,defmt,exti,time-driver-any,time \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030rc,defmt,exti,time-driver-any,time \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f070f6,defmt,exti,time-driver-any,time \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f078vb,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f042g4,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f072c8,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f401ve,defmt,exti,time-driver-any \

embassy-stm32/Cargo.toml

@@ -68,7 +68,7 @@ rand_core = "0.6.3"
 sdio-host = "0.5.0"
 critical-section = "1.1"
 #stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8a3ad0b738292ae40af201d79b28db60fe876e11" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7734584b2007766b1c5a6a7f2654fdb442fa211a" }
 vcell = "0.1.3"
 bxcan = "0.7.0"
 nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
 #stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8a3ad0b738292ae40af201d79b28db60fe876e11", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7734584b2007766b1c5a6a7f2654fdb442fa211a", default-features = false, features = ["metadata"]}
 
 
 [features]

embassy-stm32/src/rcc/f0.rs

@@ -1,27 +1,64 @@
-use stm32_metapac::flash::vals::Latency;
+use crate::pac::flash::vals::Latency;
-
+use crate::pac::rcc::vals::Pllsrc;
-use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Sw, Usbsw};
+pub use crate::pac::rcc::vals::{
+    Hpre as AHBPrescaler, Pllmul as PllMul, Ppre as APBPrescaler, Prediv as PllPreDiv, Sw as Sysclk,
+};
 use crate::pac::{FLASH, RCC};
 use crate::time::Hertz;
 
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(8_000_000);
 
-/// Configuration of the clocks
+#[derive(Clone, Copy, Eq, PartialEq)]
-///
+pub enum HseMode {
-/// hse takes precedence over hsi48 if both are enabled
+    /// crystal/ceramic oscillator (HSEBYP=0)
+    Oscillator,
+    /// external analog clock (low swing) (HSEBYP=1)
+    Bypass,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hse {
+    /// HSE frequency.
+    pub freq: Hertz,
+    /// HSE mode.
+    pub mode: HseMode,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum PllSource {
+    HSE,
+    HSI,
+    #[cfg(rcc_f0v4)]
+    HSI48,
+}
+
+#[derive(Clone, Copy)]
+pub struct Pll {
+    pub src: PllSource,
+
+    /// PLL pre-divider.
+    ///
+    /// On some chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
+    pub prediv: PllPreDiv,
+
+    /// PLL multiplication factor.
+    pub mul: PllMul,
+}
+
+/// Clocks configutation
 #[non_exhaustive]
 pub struct Config {
-    pub hse: Option<Hertz>,
+    pub hsi: bool,
-    pub bypass_hse: bool,
+    pub hse: Option<Hse>,
-    pub usb_pll: bool,
-
     #[cfg(crs)]
     pub hsi48: Option<super::Hsi48Config>,
+    pub sys: Sysclk,
 
-    pub sys_ck: Option<Hertz>,
+    pub pll: Option<Pll>,
-    pub hclk: Option<Hertz>,
+
-    pub pclk: Option<Hertz>,
+    pub ahb_pre: AHBPrescaler,
+    pub apb1_pre: APBPrescaler,
 
     pub ls: super::LsConfig,
 }
@@ -29,168 +66,167 @@ pub struct Config {
 impl Default for Config {
     fn default() -> Self {
         Self {
-            hse: Default::default(),
+            hsi: true,
-            bypass_hse: Default::default(),
+            hse: None,
-            usb_pll: Default::default(),
             #[cfg(crs)]
             hsi48: Some(Default::default()),
-            sys_ck: Default::default(),
+            sys: Sysclk::HSI,
-            hclk: Default::default(),
+            pll: None,
-            pclk: Default::default(),
+            ahb_pre: AHBPrescaler::DIV1,
+            apb1_pre: APBPrescaler::DIV1,
             ls: Default::default(),
         }
     }
 }
 
+/// Initialize and Set the clock frequencies
 pub(crate) unsafe fn init(config: Config) {
-    let sysclk = config.sys_ck.map(|v| v.0).unwrap_or(HSI_FREQ.0);
+    // Configure HSI
+    let hsi = match config.hsi {
+        false => {
+            RCC.cr().modify(|w| w.set_hsion(false));
+            None
+        }
+        true => {
+            RCC.cr().modify(|w| w.set_hsion(true));
+            while !RCC.cr().read().hsirdy() {}
+            Some(HSI_FREQ)
+        }
+    };
 
+    // Configure HSE
+    let hse = match config.hse {
+        None => {
+            RCC.cr().modify(|w| w.set_hseon(false));
+            None
+        }
+        Some(hse) => {
+            match hse.mode {
+                HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
+                HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
+            }
+
+            RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
+            RCC.cr().modify(|w| w.set_hseon(true));
+            while !RCC.cr().read().hserdy() {}
+            Some(hse.freq)
+        }
+    };
+
+    // configure HSI48
     #[cfg(crs)]
     let hsi48 = config.hsi48.map(|config| super::init_hsi48(config));
     #[cfg(not(crs))]
     let hsi48: Option<Hertz> = None;
 
-    let (src_clk, use_hsi48) = config.hse.map(|v| (v.0, false)).unwrap_or_else(|| {
+    // Enable PLL
-        if hsi48.is_some() {
+    let pll = config.pll.map(|pll| {
-            return (48_000_000, true);
+        let (src_val, src_freq) = match pll.src {
-        }
+            #[cfg(not(any(rcc_f0v1, rcc_f0v2)))]
-        (HSI_FREQ.0, false)
+            PllSource::HSI => (Pllsrc::HSI_DIV_PREDIV, unwrap!(hsi)),
-    });
+            #[cfg(any(rcc_f0v1, rcc_f0v2))]
+            PllSource::HSI => {
+                if pll.prediv != PllPreDiv::DIV2 {
+                    panic!("if PLL source is HSI, PLL prediv must be 2.");
+                }
+                (Pllsrc::HSI_DIV2, unwrap!(hsi))
+            }
+            PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)),
+            #[cfg(rcc_f0v4)]
+            PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)),
+        };
+        let in_freq = src_freq / pll.prediv;
+        assert!(max::PLL_IN.contains(&in_freq));
+        let out_freq = in_freq * pll.mul;
+        assert!(max::PLL_OUT.contains(&out_freq));
 
-    let (pllmul_bits, real_sysclk) = if sysclk == src_clk {
+        RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv));
-        (None, sysclk)
+        RCC.cfgr().modify(|w| {
-    } else {
+            w.set_pllmul(pll.mul);
-        let prediv = if config.hse.is_some() { 1 } else { 2 };
+            w.set_pllsrc(src_val);
-        let pllmul = (2 * prediv * sysclk + src_clk) / src_clk / 2;
-        let pllmul = pllmul.max(2).min(16);
-
-        let pllmul_bits = pllmul as u8 - 2;
-        let real_sysclk = pllmul * src_clk / prediv;
-        (Some(pllmul_bits), real_sysclk)
-    };
-
-    let hpre_bits = config
-        .hclk
-        .map(|hclk| match real_sysclk / hclk.0 {
-            0 => unreachable!(),
-            1 => 0b0111,
-            2 => 0b1000,
-            3..=5 => 0b1001,
-            6..=11 => 0b1010,
-            12..=39 => 0b1011,
-            40..=95 => 0b1100,
-            96..=191 => 0b1101,
-            192..=383 => 0b1110,
-            _ => 0b1111,
-        })
-        .unwrap_or(0b0111);
-    let hclk = real_sysclk / (1 << (hpre_bits - 0b0111));
-
-    let ppre_bits = config
-        .pclk
-        .map(|pclk| match hclk / pclk.0 {
-            0 => unreachable!(),
-            1 => 0b011,
-            2 => 0b100,
-            3..=5 => 0b101,
-            6..=11 => 0b110,
-            _ => 0b111,
-        })
-        .unwrap_or(0b011);
-
-    let ppre: u8 = 1 << (ppre_bits - 0b011);
-    let pclk = hclk / u32::from(ppre);
-
-    let timer_mul = if ppre == 1 { 1 } else { 2 };
-
-    FLASH.acr().write(|w| {
-        w.set_latency(if real_sysclk <= 24_000_000 {
-            Latency::WS0
-        } else {
-            Latency::WS1
         });
-    });
-
-    match (config.hse.is_some(), use_hsi48) {
-        (true, _) => {
-            RCC.cr().modify(|w| {
-                w.set_csson(true);
-                w.set_hseon(true);
-                w.set_hsebyp(config.bypass_hse);
-            });
-            while !RCC.cr().read().hserdy() {}
-
-            if pllmul_bits.is_some() {
-                RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSE_DIV_PREDIV))
-            }
-        }
-        // use_hsi48 will always be false for stm32f0x0
-        #[cfg(not(stm32f0x0))]
-        (false, true) => {
-            RCC.cr2().modify(|w| w.set_hsi48on(true));
-            while !RCC.cr2().read().hsi48rdy() {}
-
-            if pllmul_bits.is_some() {
-                RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSI48_DIV_PREDIV))
-            }
-        }
-        _ => {
-            RCC.cr().modify(|w| w.set_hsion(true));
-            while !RCC.cr().read().hsirdy() {}
-
-            if pllmul_bits.is_some() {
-                RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSI_DIV2))
-            }
-        }
-    }
-
-    if config.usb_pll {
-        RCC.cfgr3().modify(|w| w.set_usbsw(Usbsw::PLL1_P));
-    }
-    // TODO: Option to use CRS (Clock Recovery)
-
-    if let Some(pllmul_bits) = pllmul_bits {
-        RCC.cfgr().modify(|w| w.set_pllmul(Pllmul::from_bits(pllmul_bits)));
-
         RCC.cr().modify(|w| w.set_pllon(true));
         while !RCC.cr().read().pllrdy() {}
 
-        RCC.cfgr().modify(|w| {
+        out_freq
-            w.set_ppre(Ppre::from_bits(ppre_bits));
+    });
-            w.set_hpre(Hpre::from_bits(hpre_bits));
-            w.set_sw(Sw::PLL1_P)
-        });
-    } else {
-        RCC.cfgr().modify(|w| {
-            w.set_ppre(Ppre::from_bits(ppre_bits));
-            w.set_hpre(Hpre::from_bits(hpre_bits));
 
-            if config.hse.is_some() {
+    // Configure sysclk
-                w.set_sw(Sw::HSE);
+    let sys = match config.sys {
-            } else if use_hsi48 {
+        Sysclk::HSI => unwrap!(hsi),
-                #[cfg(not(stm32f0x0))]
+        Sysclk::HSE => unwrap!(hse),
-                w.set_sw(Sw::HSI48);
+        Sysclk::PLL1_P => unwrap!(pll),
-            } else {
+        #[cfg(rcc_f0v4)]
-                w.set_sw(Sw::HSI)
+        Sysclk::HSI48 => unwrap!(hsi48),
-            }
+        #[allow(unreachable_patterns)]
-        })
+        _ => unreachable!(),
-    }
+    };
+
+    let hclk = sys / config.ahb_pre;
+    let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
+
+    assert!(max::HCLK.contains(&hclk));
+    assert!(max::PCLK1.contains(&pclk1));
+
+    // Set latency based on HCLK frquency
+    let latency = match hclk.0 {
+        ..=24_000_000 => Latency::WS0,
+        _ => Latency::WS1,
+    };
+    FLASH.acr().modify(|w| {
+        w.set_latency(latency);
+        w.set_prftbe(true);
+    });
+
+    // Set prescalers
+    // CFGR has been written before (PLL, PLL48) don't overwrite these settings
+    RCC.cfgr().modify(|w| {
+        w.set_ppre(config.apb1_pre);
+        w.set_hpre(config.ahb_pre);
+    });
+
+    // Wait for the new prescalers to kick in
+    // "The clocks are divided with the new prescaler factor from
+    //  1 to 16 AHB cycles after write"
+    cortex_m::asm::delay(16);
+
+    // CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
+    RCC.cfgr().modify(|w| w.set_sw(config.sys));
+    while RCC.cfgr().read().sws() != config.sys {}
 
     let rtc = config.ls.init();
 
     set_clocks!(
-        hsi: None,
+        hsi: hsi,
-        lse: None,
+        hse: hse,
-        sys: Some(Hertz(real_sysclk)),
+        pll1_p: pll,
-        pclk1: Some(Hertz(pclk)),
+        sys: Some(sys),
-        pclk2: Some(Hertz(pclk)),
+        pclk1: Some(pclk1),
-        pclk1_tim: Some(Hertz(pclk * timer_mul)),
+        pclk2: Some(pclk1),
-        pclk2_tim: Some(Hertz(pclk * timer_mul)),
+        pclk1_tim: Some(pclk1_tim),
-        hclk1: Some(Hertz(hclk)),
+        pclk2_tim: Some(pclk1_tim),
-        rtc: rtc,
+        hclk1: Some(hclk),
+        #[cfg(all(not(rcc_f37), adc3_common))]
+        adc34: Some(adc34),
+        #[cfg(stm32f334)]
+        hrtim: hrtim,
         hsi48: hsi48,
-
+        rtc: rtc,
-        // TODO:
+        lse: None,
-        pll1_p: None,
     );
 }
+
+mod max {
+    use core::ops::RangeInclusive;
+
+    use crate::time::Hertz;
+
+    pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(32_000_000);
+    pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(32_000_000);
+
+    pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
+    pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
+
+    pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(24_000_000);
+    pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(48_000_000);
+}

embassy-stm32/src/rcc/mco.rs

@@ -4,7 +4,7 @@ use embassy_hal_internal::into_ref;
 
 use crate::gpio::sealed::AFType;
 use crate::gpio::Speed;
-#[cfg(not(any(stm32f1, rcc_f3v1, rcc_f37)))]
+#[cfg(not(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37)))]
 pub use crate::pac::rcc::vals::Mcopre as McoPrescaler;
 #[cfg(not(any(rcc_f2, rcc_f410, rcc_f4, rcc_f7, rcc_h50, rcc_h5, rcc_h7ab, rcc_h7rm0433, rcc_h7)))]
 pub use crate::pac::rcc::vals::Mcosel as McoSource;
@@ -13,7 +13,7 @@ pub use crate::pac::rcc::vals::{Mco1sel as Mco1Source, Mco2sel as Mco2Source};
 use crate::pac::RCC;
 use crate::{peripherals, Peripheral};
 
-#[cfg(any(stm32f1, rcc_f3v1, rcc_f37))]
+#[cfg(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37))]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
 pub enum McoPrescaler {
     DIV1,
@@ -43,7 +43,7 @@ macro_rules! impl_peri {
 
                 r.modify(|w| {
                     w.$set_source(source);
-                    #[cfg(not(any(stm32f1, rcc_f3v1, rcc_f37)))]
+                    #[cfg(not(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37)))]
                     w.$set_prescaler(_prescaler);
                 });
             }

embassy-stm32/src/rcc/mod.rs

@@ -18,17 +18,17 @@ mod hsi48;
 #[cfg(crs)]
 pub use hsi48::*;
 
-#[cfg_attr(rcc_f0, path = "f0.rs")]
+#[cfg_attr(stm32f0, path = "f0.rs")]
-#[cfg_attr(any(stm32f1), path = "f1.rs")]
+#[cfg_attr(stm32f1, path = "f1.rs")]
-#[cfg_attr(any(stm32f3), path = "f3.rs")]
+#[cfg_attr(stm32f3, path = "f3.rs")]
 #[cfg_attr(any(stm32f2, stm32f4, stm32f7), path = "f.rs")]
-#[cfg_attr(rcc_c0, path = "c0.rs")]
+#[cfg_attr(stm32c0, path = "c0.rs")]
-#[cfg_attr(rcc_g0, path = "g0.rs")]
+#[cfg_attr(stm32g0, path = "g0.rs")]
-#[cfg_attr(rcc_g4, path = "g4.rs")]
+#[cfg_attr(stm32g4, path = "g4.rs")]
 #[cfg_attr(any(stm32h5, stm32h7), path = "h.rs")]
 #[cfg_attr(any(stm32l0, stm32l1, stm32l4, stm32l5, stm32wb, stm32wl), path = "l.rs")]
-#[cfg_attr(rcc_u5, path = "u5.rs")]
+#[cfg_attr(stm32u5, path = "u5.rs")]
-#[cfg_attr(rcc_wba, path = "wba.rs")]
+#[cfg_attr(stm32wba, path = "wba.rs")]
 mod _version;
 
 pub use _version::*;