mirror of
https://github.com/embassy-rs/embassy.git
synced 2024-11-22 06:42:32 +00:00
commit
c7c6b0b464
@ -145,6 +145,15 @@ with open(output_file, 'w') as f:
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if re.match('EXTI', irq):
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exti_interrupts.append(irq)
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if block_mod == 'dac':
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f.write(f'impl_dac!({name});')
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if 'dac_out1' in peri:
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pin = peri['dac_out1']
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f.write(f'impl_dac_pin!({name}, 1, {pin});')
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if 'dac_out2' in peri:
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pin = peri['dac_out2']
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f.write(f'impl_dac_pin!({name}, 2, {pin});')
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if not custom_singletons:
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singletons.append(name)
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48
embassy-stm32/src/dac/mod.rs
Normal file
48
embassy-stm32/src/dac/mod.rs
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@ -0,0 +1,48 @@
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#![macro_use]
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#[cfg_attr(dac_v2, path = "v2.rs")]
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mod _version;
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use crate::gpio::NoPin;
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pub use _version::*;
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pub(crate) mod sealed {
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use super::*;
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use crate::gpio::{OptionalPin, Pin};
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pub trait Instance {
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fn regs() -> &'static crate::pac::dac::Dac;
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}
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pub trait DacPin<T: Instance, const C: u8>: OptionalPin {}
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}
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pub trait Instance: sealed::Instance + 'static {}
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pub trait DacPin<T: Instance, const C: u8>: sealed::DacPin<T, C> + 'static {}
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impl<T: Instance, const C: u8> DacPin<T, C> for NoPin {}
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impl<T: Instance, const C: u8> sealed::DacPin<T, C> for NoPin {}
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macro_rules! impl_dac {
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($inst:ident) => {
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impl crate::dac::sealed::Instance for peripherals::$inst {
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fn regs() -> &'static crate::pac::dac::Dac {
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&crate::pac::$inst
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}
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}
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impl crate::dac::Instance for peripherals::$inst {}
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};
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}
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macro_rules! impl_dac_pin {
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($inst:ident, $channel:expr, $pin:ident ) => {
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impl crate::dac::DacPin<peripherals::$inst, $channel> for peripherals::$pin {}
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impl crate::dac::sealed::DacPin<peripherals::$inst, $channel> for peripherals::$pin {
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//fn af_num(&self) -> u8 {
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//$af
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//}
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}
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};
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}
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284
embassy-stm32/src/dac/v2.rs
Normal file
284
embassy-stm32/src/dac/v2.rs
Normal file
@ -0,0 +1,284 @@
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use crate::dac::{DacPin, Instance};
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use crate::gpio::Pin;
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use crate::gpio::{AnyPin, OptionalPin};
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use crate::pac::dac;
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use embassy_extras::unborrow;
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pub enum Error {
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UnconfiguredChannel,
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InvalidValue,
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}
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pub enum Channel {
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Ch1,
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Ch2,
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}
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pub enum Ch1Trigger {
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Tim6,
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Tim3,
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Tim7,
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Tim15,
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Tim2,
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Exti9,
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Software,
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}
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impl Ch1Trigger {
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fn tsel(&self) -> dac::vals::Tsel1 {
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match self {
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Ch1Trigger::Tim6 => dac::vals::Tsel1::TIM6_TRGO,
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Ch1Trigger::Tim3 => dac::vals::Tsel1::TIM3_TRGO,
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Ch1Trigger::Tim7 => dac::vals::Tsel1::TIM7_TRGO,
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Ch1Trigger::Tim15 => dac::vals::Tsel1::TIM15_TRGO,
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Ch1Trigger::Tim2 => dac::vals::Tsel1::TIM2_TRGO,
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Ch1Trigger::Exti9 => dac::vals::Tsel1::EXTI9,
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Ch1Trigger::Software => dac::vals::Tsel1::SOFTWARE,
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}
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}
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}
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pub enum Ch2Trigger {
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Tim6,
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Tim8,
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Tim7,
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Tim5,
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Tim2,
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Tim4,
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Exti9,
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Software,
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}
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impl Ch2Trigger {
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fn tsel(&self) -> dac::vals::Tsel2 {
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match self {
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Ch2Trigger::Tim6 => dac::vals::Tsel2::TIM6_TRGO,
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Ch2Trigger::Tim8 => dac::vals::Tsel2::TIM8_TRGO,
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Ch2Trigger::Tim7 => dac::vals::Tsel2::TIM7_TRGO,
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Ch2Trigger::Tim5 => dac::vals::Tsel2::TIM5_TRGO,
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Ch2Trigger::Tim2 => dac::vals::Tsel2::TIM2_TRGO,
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Ch2Trigger::Tim4 => dac::vals::Tsel2::TIM4_TRGO,
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Ch2Trigger::Exti9 => dac::vals::Tsel2::EXTI9,
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Ch2Trigger::Software => dac::vals::Tsel2::SOFTWARE,
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}
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}
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}
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pub enum Alignment {
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Left,
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Right,
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}
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pub enum Value {
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Bit8(u8),
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Bit12(u16, Alignment),
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}
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pub struct Dac<'d, T: Instance> {
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//peri: T,
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ch1: Option<AnyPin>,
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ch2: Option<AnyPin>,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance> Dac<'d, T> {
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pub fn new(
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peri: impl Unborrow<Target = T> + 'd,
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ch1: impl Unborrow<Target = impl DacPin<T, 1>>,
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ch2: impl Unborrow<Target = impl DacPin<T, 2>>,
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) -> Self {
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unborrow!(peri);
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unborrow!(ch1, ch2);
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let ch1 = ch1.degrade_optional();
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if ch1.is_some() {
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_en1(true);
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});
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}
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}
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let ch2 = ch2.degrade_optional();
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if ch2.is_some() {
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_en2(true);
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});
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}
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}
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let mut dac = Self {
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ch1,
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ch2,
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phantom: PhantomData,
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};
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dac
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}
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pub fn enable_channel(&mut self, ch: Channel) -> Result<(), Error> {
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match ch {
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Channel::Ch1 => {
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if self.ch1.is_none() {
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Err(Error::UnconfiguredChannel)
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} else {
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_en1(true);
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});
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}
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Ok(())
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}
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}
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Channel::Ch2 => {
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if self.ch2.is_none() {
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Err(Error::UnconfiguredChannel)
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} else {
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_en2(true);
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});
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}
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Ok(())
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}
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}
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}
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}
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pub fn disable_channel(&mut self, ch: Channel) -> Result<(), Error> {
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match ch {
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Channel::Ch1 => {
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if self.ch1.is_none() {
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Err(Error::UnconfiguredChannel)
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} else {
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_en1(true);
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});
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}
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Ok(())
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}
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}
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Channel::Ch2 => {
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if self.ch2.is_none() {
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Err(Error::UnconfiguredChannel)
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} else {
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_en2(true);
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});
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}
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Ok(())
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}
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}
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}
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}
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pub fn select_trigger_ch1(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
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if self.ch1.is_none() {
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return Err(Error::UnconfiguredChannel);
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}
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self.disable_channel(Channel::Ch1);
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_tsel1(trigger.tsel());
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})
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}
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Ok(())
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}
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pub fn select_trigger_ch2(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
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if self.ch2.is_none() {
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return Err(Error::UnconfiguredChannel);
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}
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self.disable_channel(Channel::Ch2);
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_tsel2(trigger.tsel());
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})
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}
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Ok(())
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}
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pub fn trigger(&mut self, ch: Channel) -> Result<(), Error> {
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match ch {
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Channel::Ch1 => {
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if self.ch1.is_none() {
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Err(Error::UnconfiguredChannel)
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} else {
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unsafe {
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T::regs().swtrigr().write(|reg| {
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reg.set_swtrig1(true);
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});
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}
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Ok(())
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}
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}
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Channel::Ch2 => {
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if self.ch2.is_none() {
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Err(Error::UnconfiguredChannel)
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} else {
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unsafe {
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T::regs().swtrigr().write(|reg| {
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reg.set_swtrig2(true);
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});
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}
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Ok(())
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}
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}
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}
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}
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pub fn trigger_all(&mut self) {
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unsafe {
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T::regs().swtrigr().write(|reg| {
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reg.set_swtrig1(true);
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reg.set_swtrig2(true);
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})
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}
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}
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pub fn set(&mut self, ch: Channel, value: Value) -> Result<(), Error> {
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match ch {
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Channel::Ch1 => {
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if self.ch1.is_none() {
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Err(Error::UnconfiguredChannel)
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} else {
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match value {
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Value::Bit8(v) => unsafe {
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T::regs().dhr8r1().write(|reg| reg.set_dacc1dhr(v));
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},
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Value::Bit12(v, Alignment::Left) => unsafe {
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T::regs().dhr12l1().write(|reg| reg.set_dacc1dhr(v));
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},
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Value::Bit12(v, Alignment::Right) => unsafe {
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T::regs().dhr12r1().write(|reg| reg.set_dacc1dhr(v));
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},
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}
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Ok(())
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}
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}
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Channel::Ch2 => {
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if self.ch2.is_none() {
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Err(Error::UnconfiguredChannel)
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} else {
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match value {
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Value::Bit8(v) => unsafe {
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T::regs().dhr8r2().write(|reg| reg.set_dacc2dhr(v));
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},
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Value::Bit12(v, Alignment::Left) => unsafe {
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T::regs().dhr12l2().write(|reg| reg.set_dacc2dhr(v));
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},
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Value::Bit12(v, Alignment::Right) => unsafe {
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T::regs().dhr12r2().write(|reg| reg.set_dacc2dhr(v));
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},
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}
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Ok(())
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}
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}
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}
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}
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}
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@ -23,6 +23,8 @@ pub mod rcc;
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// Sometimes-present hardware
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#[cfg(timer)]
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pub mod clock;
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#[cfg(dac)]
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pub mod dac;
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#[cfg(dma)]
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pub mod dma;
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#[cfg(i2c)]
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@ -1 +1 @@
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Subproject commit 64220ffdbf55b802f063ab209cdd7a788c95ca57
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Subproject commit dfc67fe255e1e70101e9f1e3fb8b4fd8bb37362f
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