nordic-dev.net/embassy
2
0
Fork 0
mirror of https://github.com/embassy-rs/embassy.git synced 2024-11-22 14:53:03 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #2292 from sourcebox/stm32h7-rm0468-fixes

Browse Source 
[embassy-stm32]: Fixes for STM32H7 series MCUs referenced in RM0468
This commit is contained in:
Dario Nieuwenhuis 2023-12-15 23:02:42 +00:00 committed by GitHub
commit b966f55883
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 40 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
embassy-stm32/src/rcc/h.rs
View File

@ -70,7 +70,9 @@ pub struct Pll {
pub mul: PllMul,
/// PLL P division factor. If None, PLL P output is disabled.
/// On PLL1, it must be even (in particular, it cannot be 1.)
/// On PLL1, it must be even for most series (in particular,
/// it cannot be 1 in series other than STM32H723/733,
/// STM32H725/735 and STM32H730.)
pub divp: Option<PllDiv>,
/// PLL Q division factor. If None, PLL Q output is disabled.
pub divq: Option<PllDiv>,
@ -476,7 +478,14 @@ pub(crate) unsafe fn init(config: Config) {
VoltageScale::Scale2 => (Hertz(160_000_000), Hertz(160_000_000), Hertz(80_000_000)),
VoltageScale::Scale3 => (Hertz(88_000_000), Hertz(88_000_000), Hertz(44_000_000)),
};
#[cfg(all(stm32h7, not(pwr_h7rm0455)))]
#[cfg(pwr_h7rm0468)]
let (d1cpre_clk_max, hclk_max, pclk_max) = match config.voltage_scale {
VoltageScale::Scale0 => (Hertz(520_000_000), Hertz(275_000_000), Hertz(137_500_000)),
VoltageScale::Scale1 => (Hertz(400_000_000), Hertz(200_000_000), Hertz(100_000_000)),
VoltageScale::Scale2 => (Hertz(300_000_000), Hertz(150_000_000), Hertz(75_000_000)),
VoltageScale::Scale3 => (Hertz(170_000_000), Hertz(85_000_000), Hertz(42_500_000)),
};
#[cfg(all(stm32h7, not(any(pwr_h7rm0455, pwr_h7rm0468))))]
let (d1cpre_clk_max, hclk_max, pclk_max) = match config.voltage_scale {
VoltageScale::Scale0 => (Hertz(480_000_000), Hertz(240_000_000), Hertz(120_000_000)),
VoltageScale::Scale1 => (Hertz(400_000_000), Hertz(200_000_000), Hertz(100_000_000)),
@ -729,9 +738,12 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
let p = config.divp.map(|div| {
if num == 0 {
// on PLL1, DIVP must be even.
// on PLL1, DIVP must be even for most series.
// The enum value is 1 less than the divider, so check it's odd.
#[cfg(not(pwr_h7rm0468))]
assert!(div.to_bits() % 2 == 1);
#[cfg(pwr_h7rm0468)]
assert!(div.to_bits() % 2 == 1 || div.to_bits() == 0);
}
vco_clk / div
@ -820,7 +832,7 @@ fn flash_setup(clk: Hertz, vos: VoltageScale) {
_ => unreachable!(),
};
#[cfg(flash_h7)]
#[cfg(all(flash_h7, not(pwr_h7rm0468)))]
let (latency, wrhighfreq) = match (vos, clk.0) {
// VOS 0 range VCORE 1.26V - 1.40V
(VoltageScale::Scale0, ..=70_000_000) => (0, 0),
@ -849,6 +861,30 @@ fn flash_setup(clk: Hertz, vos: VoltageScale) {
_ => unreachable!(),
};
// See RM0468 Rev 3 Table 16. FLASH recommended number of wait
// states and programming delay
#[cfg(all(flash_h7, pwr_h7rm0468))]
let (latency, wrhighfreq) = match (vos, clk.0) {
// VOS 0 range VCORE 1.26V - 1.40V
(VoltageScale::Scale0, ..=70_000_000) => (0, 0),
(VoltageScale::Scale0, ..=140_000_000) => (1, 1),
(VoltageScale::Scale0, ..=210_000_000) => (2, 2),
(VoltageScale::Scale0, ..=275_000_000) => (3, 3),
// VOS 1 range VCORE 1.15V - 1.26V
(VoltageScale::Scale1, ..=67_000_000) => (0, 0),
(VoltageScale::Scale1, ..=133_000_000) => (1, 1),
(VoltageScale::Scale1, ..=200_000_000) => (2, 2),
// VOS 2 range VCORE 1.05V - 1.15V
(VoltageScale::Scale2, ..=50_000_000) => (0, 0),
(VoltageScale::Scale2, ..=100_000_000) => (1, 1),
(VoltageScale::Scale2, ..=150_000_000) => (2, 2),
// VOS 3 range VCORE 0.95V - 1.05V
(VoltageScale::Scale3, ..=35_000_000) => (0, 0),
(VoltageScale::Scale3, ..=70_000_000) => (1, 1),
(VoltageScale::Scale3, ..=85_000_000) => (2, 2),
_ => unreachable!(),
};
// See RM0455 Rev 10 Table 16. FLASH recommended number of wait
// states and programming delay
#[cfg(flash_h7ab)]