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fix: build issues

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elagil 2025-03-30 13:52:55 +02:00
parent 70571996ad
commit b3ef0ffc2f
2 changed files with 13 additions and 17 deletions
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12
embassy-stm32/src/dma/gpdma/mod.rs
View File

@ -382,23 +382,21 @@ impl AnyChannel {
/// Linked-list DMA transfer.
#[must_use = "futures do nothing unless you `.await` or poll them"]
pub struct LinkedListTransfer<'a, const ITEM_COUNT: usize> {
channel: PeripheralRef<'a, AnyChannel>,
channel: Peri<'a, AnyChannel>,
}
impl<'a, const ITEM_COUNT: usize> LinkedListTransfer<'a, ITEM_COUNT> {
/// Create a new linked-list transfer.
pub unsafe fn new_linked_list<const N: usize>(
channel: impl Peripheral<P = impl Channel> + 'a,
channel: Peri<'a, impl Channel>,
table: Table<ITEM_COUNT>,
options: TransferOptions,
) -> Self {
into_ref!(channel);
Self::new_inner_linked_list(channel.map_into(), table, options)
Self::new_inner_linked_list(channel.into(), table, options)
}
unsafe fn new_inner_linked_list(
channel: PeripheralRef<'a, AnyChannel>,
channel: Peri<'a, AnyChannel>,
table: Table<ITEM_COUNT>,
options: TransferOptions,
) -> Self {
@ -576,7 +574,7 @@ impl<'a> Transfer<'a> {
assert!(mem_len > 0 && mem_len <= 0xFFFF);
channel.configure(
_request,
request,
dir,
peri_addr,
mem_addr,

18
embassy-stm32/src/dma/gpdma/ringbuffered.rs
View File

@ -5,7 +5,7 @@ use core::future::poll_fn;
use core::sync::atomic::{fence, Ordering};
use core::task::Waker;
use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
use embassy_hal_internal::Peri;
use super::{AnyChannel, TransferOptions, STATE};
use crate::dma::gpdma::linked_list::{LinearItem, RunMode, Table};
@ -13,7 +13,7 @@ use crate::dma::ringbuffer::{DmaCtrl, Error, ReadableDmaRingBuffer, WritableDmaR
use crate::dma::word::Word;
use crate::dma::{Channel, Request};
struct DmaCtrlImpl<'a>(PeripheralRef<'a, AnyChannel>);
struct DmaCtrlImpl<'a>(Peri<'a, AnyChannel>);
impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
fn get_remaining_transfers(&self) -> usize {
@ -48,7 +48,7 @@ impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
/// Ringbuffer for receiving data using GPDMA linked-list mode.
pub struct ReadableRingBuffer<'a, W: Word> {
channel: PeripheralRef<'a, AnyChannel>,
channel: Peri<'a, AnyChannel>,
ringbuf: ReadableDmaRingBuffer<'a, W>,
table: Table<2>,
}
@ -58,14 +58,13 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
///
/// Transfer options are applied to the individual linked list items.
pub unsafe fn new(
channel: impl Peripheral<P = impl Channel> + 'a,
channel: Peri<'a, impl Channel>,
request: Request,
peri_addr: *mut W,
buffer: &'a mut [W],
_options: TransferOptions,
) -> Self {
into_ref!(channel);
let channel: PeripheralRef<'a, AnyChannel> = channel.map_into();
let channel: Peri<'a, AnyChannel> = channel.into();
// Buffer halves should be the same length.
let half_len = buffer.len() / 2;
@ -195,7 +194,7 @@ impl<'a, W: Word> Drop for ReadableRingBuffer<'a, W> {
/// Ringbuffer for writing data using DMA circular mode.
pub struct WritableRingBuffer<'a, W: Word> {
channel: PeripheralRef<'a, AnyChannel>,
channel: Peri<'a, AnyChannel>,
ringbuf: WritableDmaRingBuffer<'a, W>,
table: Table<2>,
}
@ -203,14 +202,13 @@ pub struct WritableRingBuffer<'a, W: Word> {
impl<'a, W: Word> WritableRingBuffer<'a, W> {
/// Create a new ring buffer.
pub unsafe fn new(
channel: impl Peripheral<P = impl Channel> + 'a,
channel: Peri<'a, impl Channel>,
request: Request,
peri_addr: *mut W,
buffer: &'a mut [W],
_options: TransferOptions,
) -> Self {
into_ref!(channel);
let channel: PeripheralRef<'a, AnyChannel> = channel.map_into();
let channel: Peri<'a, AnyChannel> = channel.into();
// Buffer halves should be the same length.
let half_len = buffer.len() / 2;