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https://github.com/embassy-rs/embassy.git
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Remove data length from transfer config
Remove non hal traits Fix function comments
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@ -113,8 +113,6 @@ pub struct TransferConfig {
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/// Data width (DMODE)
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pub dwidth: OspiWidth,
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/// Length of data
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pub data_len: Option<usize>,
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/// Data buffer
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pub ddtr: bool,
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@ -141,7 +139,6 @@ impl Default for TransferConfig {
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abdtr: false,
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dwidth: OspiWidth::NONE,
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data_len: None,
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ddtr: false,
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dummy: DummyCycles::_0,
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@ -158,40 +155,6 @@ pub enum OspiError {
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InvalidCommand,
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}
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/// MultiSpi interface trait
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pub trait MultiSpiBus<Word: Copy + 'static = u8>: embedded_hal_1::spi::ErrorType {
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/// Transaction configuration for specific multispi implementation
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type Config;
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/// Command function used for a configuration operation, when no user data is
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/// supplied to or read from the target device.
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async fn command(&mut self, config: Self::Config) -> Result<(), Self::Error>;
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/// Read function used to read data from the target device following the supplied transaction
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/// configuration.
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async fn read(&mut self, data: &mut [Word], config: Self::Config) -> Result<(), Self::Error>;
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/// Write function used to send data to the target device following the supplied transaction
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/// configuration.
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async fn write(&mut self, data: &[Word], config: Self::Config) -> Result<(), Self::Error>;
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}
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impl<T: MultiSpiBus<Word> + ?Sized, Word: Copy + 'static> MultiSpiBus<Word> for &mut T {
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type Config = T::Config;
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#[inline]
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async fn command(&mut self, config: Self::Config) -> Result<(), Self::Error> {
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T::command(self, config).await
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}
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async fn read(&mut self, data: &mut [Word], config: Self::Config) -> Result<(), Self::Error> {
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T::read(self, data, config).await
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}
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async fn write(&mut self, data: &[Word], config: Self::Config) -> Result<(), Self::Error> {
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T::write(self, data, config).await
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}
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}
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/// OSPI driver.
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pub struct Ospi<'d, T: Instance, Dma> {
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_peri: PeripheralRef<'d, T>,
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@ -211,35 +174,9 @@ pub struct Ospi<'d, T: Instance, Dma> {
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width: OspiWidth,
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}
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impl embedded_hal_1::spi::Error for OspiError {
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fn kind(&self) -> ErrorKind {
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ErrorKind::Other
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}
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}
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impl<'d, T: Instance, Dma> embedded_hal_1::spi::ErrorType for Ospi<'d, T, Dma> {
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type Error = OspiError;
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}
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impl<'d, T: Instance, Dma: OctoDma<T>, W: Word> MultiSpiBus<W> for Ospi<'d, T, Dma> {
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type Config = TransferConfig;
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async fn command(&mut self, config: Self::Config) -> Result<(), Self::Error> {
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self.command(&config).await
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}
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async fn read(&mut self, data: &mut [W], config: Self::Config) -> Result<(), Self::Error> {
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self.read(data, config).await
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}
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async fn write(&mut self, data: &[W], config: Self::Config) -> Result<(), Self::Error> {
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self.write(data, config).await
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}
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}
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impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> {
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/// Create new OSPI driver for a dualspi external chip
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pub fn new_spi(
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/// Create new OSPI driver for a single spi external chip
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pub fn new_singlespi(
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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@ -422,7 +359,7 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> {
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)
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}
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/// Create new OSPI driver for two quadspi external chips
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/// Create new OSPI driver for octospi external chips
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pub fn new_octospi(
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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@ -584,7 +521,7 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> {
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}
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// Function to configure the peripheral for the requested command
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fn configure_command(&mut self, command: &TransferConfig) -> Result<(), OspiError> {
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fn configure_command(&mut self, command: &TransferConfig, data_len: Option<usize>) -> Result<(), OspiError> {
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// Check that transaction doesn't use more than hardware initialized pins
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if <enums::OspiWidth as Into<u8>>::into(command.iwidth) > <enums::OspiWidth as Into<u8>>::into(self.width)
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|| <enums::OspiWidth as Into<u8>>::into(command.adwidth) > <enums::OspiWidth as Into<u8>>::into(self.width)
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@ -614,10 +551,14 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> {
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});
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// Configure data
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if let Some(data_length) = command.data_len {
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if let Some(data_length) = data_len {
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T::REGS.dlr().write(|v| {
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v.set_dl((data_length - 1) as u32);
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})
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} else {
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T::REGS.dlr().write(|v| {
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v.set_dl((0) as u32);
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})
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}
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// Configure instruction/address/data modes
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@ -681,7 +622,7 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> {
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while T::REGS.sr().read().busy() {}
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// Need additional validation that command configuration doesn't have data set
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self.configure_command(command)?;
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self.configure_command(command, None)?;
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// Transaction initiated by setting final configuration, i.e the instruction register
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while !T::REGS.sr().read().tcf() {}
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@ -702,7 +643,7 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> {
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w.set_dmaen(false);
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});
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self.configure_command(&transaction)?;
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self.configure_command(&transaction, Some(buf.len()))?;
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if let Some(len) = transaction.data_len {
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let current_address = T::REGS.ar().read().address();
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@ -733,7 +674,7 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> {
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T::REGS.cr().modify(|w| {
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w.set_dmaen(false);
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});
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self.configure_command(&transaction)?;
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self.configure_command(&transaction, Some(buf.len()))?;
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if let Some(len) = transaction.data_len {
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T::REGS
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@ -757,7 +698,7 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> {
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where
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Dma: OctoDma<T>,
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{
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self.configure_command(&transaction)?;
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self.configure_command(&transaction, Some(buf.len()))?;
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let current_address = T::REGS.ar().read().address();
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let current_instruction = T::REGS.ir().read().instruction();
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@ -795,7 +736,7 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> {
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where
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Dma: OctoDma<T>,
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{
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self.configure_command(&transaction)?;
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self.configure_command(&transaction, Some(buf.len()))?;
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T::REGS
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.cr()
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.modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECTWRITE));
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@ -825,7 +766,7 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> {
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where
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Dma: OctoDma<T>,
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{
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self.configure_command(&transaction)?;
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self.configure_command(&transaction, Some(buf.len()))?;
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let current_address = T::REGS.ar().read().address();
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let current_instruction = T::REGS.ir().read().instruction();
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@ -863,7 +804,7 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> {
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where
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Dma: OctoDma<T>,
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{
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self.configure_command(&transaction)?;
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self.configure_command(&transaction, Some(buf.len()))?;
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T::REGS
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.cr()
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.modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECTWRITE));
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