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https://github.com/embassy-rs/embassy.git
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Merge #500
500: Low level DMA channel API. r=Dirbaio a=matoushybl This should be an improved version of the PR by `@theunkn0wn1.` Co-authored-by: Joshua Salzedo <joshuasalzedo@gmail.com> Co-authored-by: Matous Hybl <hyblmatous@gmail.com> Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
This commit is contained in:
bors[bot]
GitHub
commit
b0da4dfa8c
@ -1,20 +1,29 @@
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#![macro_use]
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use core::future::Future;
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use core::sync::atomic::{fence, Ordering};
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use core::task::Poll;
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use core::task::Waker;
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use embassy::interrupt::{Interrupt, InterruptExt};
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use embassy::waitqueue::AtomicWaker;
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use embassy_hal_common::drop::OnDrop;
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use futures::future::poll_fn;
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use crate::dma::{Channel, Request};
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use crate::dma::Request;
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use crate::interrupt;
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use crate::pac;
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use crate::pac::bdma::vals;
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use crate::rcc::sealed::RccPeripheral;
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use super::{Word, WordSize};
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impl From<WordSize> for vals::Size {
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fn from(raw: WordSize) -> Self {
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match raw {
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WordSize::OneByte => Self::BITS8,
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WordSize::TwoBytes => Self::BITS16,
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WordSize::FourBytes => Self::BITS32,
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}
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}
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}
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const CH_COUNT: usize = pac::peripheral_count!(bdma) * 8;
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struct State {
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@ -32,92 +41,6 @@ impl State {
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static STATE: State = State::new();
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#[allow(unused)]
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pub(crate) unsafe fn do_transfer(
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dma: pac::bdma::Dma,
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channel_number: u8,
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state_number: u8,
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request: Request,
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dir: vals::Dir,
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peri_addr: *const u8,
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mem_addr: *mut u8,
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mem_len: usize,
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incr_mem: bool,
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#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
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#[cfg(dmamux)] dmamux_ch_num: u8,
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) -> impl Future<Output = ()> {
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// ndtr is max 16 bits.
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assert!(mem_len <= 0xFFFF);
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let ch = dma.ch(channel_number as _);
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// Reset status
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dma.ifcr().write(|w| {
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w.set_tcif(channel_number as _, true);
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w.set_teif(channel_number as _, true);
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});
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let on_drop = OnDrop::new(move || unsafe {
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// Disable the channel and interrupts with the default value.
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ch.cr().write(|_| ());
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// Wait for the transfer to complete when it was ongoing.
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while ch.cr().read().en() {}
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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fence(Ordering::Acquire);
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});
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#[cfg(dmamux)]
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super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
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#[cfg(bdma_v2)]
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critical_section::with(|_| {
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dma.cselr()
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.modify(|w| w.set_cs(channel_number as _, request))
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});
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::Release);
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ch.par().write_value(peri_addr as u32);
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ch.mar().write_value(mem_addr as u32);
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ch.ndtr().write(|w| w.set_ndt(mem_len as u16));
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ch.cr().write(|w| {
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w.set_psize(vals::Size::BITS8);
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w.set_msize(vals::Size::BITS8);
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if incr_mem {
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w.set_minc(vals::Inc::ENABLED);
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} else {
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w.set_minc(vals::Inc::DISABLED);
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}
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w.set_dir(dir);
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w.set_teie(true);
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w.set_tcie(true);
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w.set_en(true);
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});
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async move {
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let res = poll_fn(|cx| {
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STATE.ch_wakers[state_number as usize].register(cx.waker());
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let isr = dma.isr().read();
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// TODO handle error
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assert!(!isr.teif(channel_number as _));
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if isr.tcif(channel_number as _) {
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Poll::Ready(())
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} else {
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Poll::Pending
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}
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})
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.await;
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drop(on_drop)
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}
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}
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macro_rules! dma_num {
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(DMA1) => {
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0
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@ -136,7 +59,7 @@ unsafe fn on_irq() {
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let isr = pac::$dma.isr().read();
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let dman = dma_num!($dma);
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for chn in 0..crate::pac::dma_channels_count!($dma) {
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for chn in 0..pac::dma_channels_count!($dma) {
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let cr = pac::$dma.ch(chn).cr();
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if isr.tcif(chn) && cr.read().tcie() {
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cr.write(|_| ()); // Disable channel interrupts with the default value.
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@ -164,88 +87,84 @@ pub(crate) unsafe fn init() {
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pac::dma_channels! {
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($channel_peri:ident, $dma_peri:ident, bdma, $channel_num:expr, $dmamux:tt) => {
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impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {}
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impl Channel for crate::peripherals::$channel_peri
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{
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type ReadFuture<'a> = impl Future<Output = ()> + 'a;
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type WriteFuture<'a> = impl Future<Output = ()> + 'a;
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impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {
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fn read<'a>(
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&'a mut self,
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request: Request,
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src: *mut u8,
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buf: &'a mut [u8],
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) -> Self::ReadFuture<'a> {
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unsafe {
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do_transfer(
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crate::pac::$dma_peri,
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$channel_num,
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(dma_num!($dma_peri) * 8) + $channel_num,
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request,
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vals::Dir::FROMPERIPHERAL,
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src,
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buf.as_mut_ptr(),
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buf.len(),
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true,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
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)
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}
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unsafe fn start_write<W: Word>(&mut self, request: Request, buf: &[W], reg_addr: *mut W) {
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low_level_api::start_transfer(
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pac::$dma_peri,
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$channel_num,
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#[cfg(any(bdma_v2, dmamux))]
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request,
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vals::Dir::FROMMEMORY,
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reg_addr as *const u32,
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buf.as_ptr() as *mut u32,
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buf.len(),
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true,
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vals::Size::from(W::bits()),
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
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);
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}
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fn write<'a>(
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&'a mut self,
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request: Request,
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buf: &'a [u8],
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dst: *mut u8,
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) -> Self::WriteFuture<'a> {
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unsafe {
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do_transfer(
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crate::pac::$dma_peri,
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$channel_num,
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(dma_num!($dma_peri) * 8) + $channel_num,
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request,
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vals::Dir::FROMMEMORY,
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dst,
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buf.as_ptr() as *mut u8,
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buf.len(),
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true,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
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)
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}
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unsafe fn start_write_repeated<W: Word>(&mut self, request: Request, repeated: W, count: usize, reg_addr: *mut W) {
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let buf = [repeated];
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low_level_api::start_transfer(
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pac::$dma_peri,
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$channel_num,
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#[cfg(any(bdma_v2, dmamux))]
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request,
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vals::Dir::FROMMEMORY,
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reg_addr as *const u32,
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buf.as_ptr() as *mut u32,
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count,
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false,
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vals::Size::from(W::bits()),
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
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)
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}
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fn write_x<'a>(
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&'a mut self,
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request: Request,
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word: &u8,
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count: usize,
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dst: *mut u8,
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) -> Self::WriteFuture<'a> {
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unsafe {
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do_transfer(
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crate::pac::$dma_peri,
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$channel_num,
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(dma_num!($dma_peri) * 8) + $channel_num,
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request,
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vals::Dir::FROMMEMORY,
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dst,
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word as *const u8 as *mut u8,
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count,
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false,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
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)
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}
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unsafe fn start_read<W: Word>(&mut self, request: Request, reg_addr: *mut W, buf: &mut [W]) {
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low_level_api::start_transfer(
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pac::$dma_peri,
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$channel_num,
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#[cfg(any(bdma_v2, dmamux))]
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request,
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vals::Dir::FROMPERIPHERAL,
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reg_addr as *const u32,
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buf.as_ptr() as *mut u32,
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buf.len(),
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true,
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vals::Size::from(W::bits()),
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
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);
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}
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fn request_stop(&mut self){
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unsafe {low_level_api::request_stop(pac::$dma_peri, $channel_num);}
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}
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fn is_running(&self) -> bool {
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unsafe {low_level_api::is_running(pac::$dma_peri, $channel_num)}
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}
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fn remaining_transfers(&mut self) -> u16 {
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unsafe {low_level_api::get_remaining_transfers(pac::$dma_peri, $channel_num)}
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}
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fn set_waker(&mut self, waker: &Waker) {
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unsafe {low_level_api::set_waker(dma_num!($dma_peri) * 8 + $channel_num, waker )}
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}
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}
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impl crate::dma::Channel for crate::peripherals::$channel_peri {}
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};
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}
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@ -257,3 +176,92 @@ pac::interrupts! {
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}
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};
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}
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mod low_level_api {
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use super::*;
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pub unsafe fn start_transfer(
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dma: pac::bdma::Dma,
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channel_number: u8,
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#[cfg(any(bdma_v2, dmamux))] request: Request,
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dir: vals::Dir,
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peri_addr: *const u32,
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mem_addr: *mut u32,
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mem_len: usize,
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incr_mem: bool,
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data_size: vals::Size,
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#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
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#[cfg(dmamux)] dmamux_ch_num: u8,
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) {
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let ch = dma.ch(channel_number as _);
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reset_status(dma, channel_number);
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#[cfg(dmamux)]
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super::super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
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#[cfg(bdma_v2)]
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critical_section::with(|_| {
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dma.cselr()
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.modify(|w| w.set_cs(channel_number as _, request))
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});
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::SeqCst);
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ch.par().write_value(peri_addr as u32);
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ch.mar().write_value(mem_addr as u32);
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ch.ndtr().write(|w| w.set_ndt(mem_len as u16));
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ch.cr().write(|w| {
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w.set_psize(data_size);
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w.set_msize(data_size);
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if incr_mem {
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w.set_minc(vals::Inc::ENABLED);
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} else {
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w.set_minc(vals::Inc::DISABLED);
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}
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w.set_dir(dir);
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w.set_teie(true);
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w.set_tcie(true);
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w.set_en(true);
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});
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}
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pub unsafe fn request_stop(dma: pac::bdma::Dma, channel_number: u8) {
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reset_status(dma, channel_number);
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let ch = dma.ch(channel_number as _);
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// Disable the channel and interrupts with the default value.
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ch.cr().write(|_| ());
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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fence(Ordering::SeqCst);
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}
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|
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pub unsafe fn is_running(dma: pac::bdma::Dma, ch: u8) -> bool {
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let ch = dma.ch(ch as _);
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ch.cr().read().en()
|
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}
|
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|
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/// Gets the total remaining transfers for the channel
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/// Note: this will be zero for transfers that completed without cancellation.
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pub unsafe fn get_remaining_transfers(dma: pac::bdma::Dma, ch: u8) -> u16 {
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// get a handle on the channel itself
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let ch = dma.ch(ch as _);
|
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// read the remaining transfer count. If this is zero, the transfer completed fully.
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ch.ndtr().read().ndt()
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}
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|
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/// Sets the waker for the specified DMA channel
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pub unsafe fn set_waker(state_number: usize, waker: &Waker) {
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STATE.ch_wakers[state_number].register(waker);
|
||||
}
|
||||
|
||||
pub unsafe fn reset_status(dma: pac::bdma::Dma, channel_number: u8) {
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dma.ifcr().write(|w| {
|
||||
w.set_tcif(channel_number as _, true);
|
||||
w.set_teif(channel_number as _, true);
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,21 +1,28 @@
|
||||
use core::future::Future;
|
||||
use core::sync::atomic::{fence, Ordering};
|
||||
use core::task::Poll;
|
||||
use core::task::Waker;
|
||||
|
||||
use embassy::interrupt::{Interrupt, InterruptExt};
|
||||
use embassy::waitqueue::AtomicWaker;
|
||||
use embassy_hal_common::drop::OnDrop;
|
||||
use futures::future::poll_fn;
|
||||
|
||||
use crate::interrupt;
|
||||
use crate::pac;
|
||||
use crate::pac::dma::{regs, vals};
|
||||
use crate::rcc::sealed::RccPeripheral;
|
||||
|
||||
use super::{Channel, Request};
|
||||
use super::{Request, Word, WordSize};
|
||||
|
||||
const CH_COUNT: usize = pac::peripheral_count!(DMA) * 8;
|
||||
|
||||
impl From<WordSize> for vals::Size {
|
||||
fn from(raw: WordSize) -> Self {
|
||||
match raw {
|
||||
WordSize::OneByte => Self::BITS8,
|
||||
WordSize::TwoBytes => Self::BITS16,
|
||||
WordSize::FourBytes => Self::BITS32,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
struct State {
|
||||
ch_wakers: [AtomicWaker; CH_COUNT],
|
||||
}
|
||||
@ -31,100 +38,6 @@ impl State {
|
||||
|
||||
static STATE: State = State::new();
|
||||
|
||||
//async unsafe fn do_transfer(ch: &mut impl Channel, ch_func: u8, src: *const u8, dst: &mut [u8]) {
|
||||
|
||||
#[allow(unused)]
|
||||
pub(crate) unsafe fn do_transfer(
|
||||
dma: pac::dma::Dma,
|
||||
channel_number: u8,
|
||||
state_number: u8,
|
||||
request: Request,
|
||||
dir: vals::Dir,
|
||||
peri_addr: *const u8,
|
||||
mem_addr: *mut u8,
|
||||
mem_len: usize,
|
||||
incr_mem: bool,
|
||||
#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
|
||||
#[cfg(dmamux)] dmamux_ch_num: u8,
|
||||
) -> impl Future<Output = ()> {
|
||||
// ndtr is max 16 bits.
|
||||
assert!(mem_len <= 0xFFFF);
|
||||
|
||||
// Reset status
|
||||
let isrn = channel_number as usize / 4;
|
||||
let isrbit = channel_number as usize % 4;
|
||||
dma.ifcr(isrn).write(|w| {
|
||||
w.set_tcif(isrbit, true);
|
||||
w.set_teif(isrbit, true);
|
||||
});
|
||||
|
||||
let ch = dma.st(channel_number as _);
|
||||
|
||||
let on_drop = OnDrop::new(move || unsafe {
|
||||
// Disable the channel and interrupts with the default value.
|
||||
ch.cr().write(|_| ());
|
||||
|
||||
// Wait for the transfer to complete when it was ongoing.
|
||||
while ch.cr().read().en() {}
|
||||
|
||||
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
|
||||
fence(Ordering::Acquire);
|
||||
});
|
||||
|
||||
#[cfg(dmamux)]
|
||||
super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
|
||||
|
||||
// "Preceding reads and writes cannot be moved past subsequent writes."
|
||||
fence(Ordering::Release);
|
||||
|
||||
unsafe {
|
||||
ch.par().write_value(peri_addr as u32);
|
||||
ch.m0ar().write_value(mem_addr as u32);
|
||||
ch.ndtr().write_value(regs::Ndtr(mem_len as _));
|
||||
ch.cr().write(|w| {
|
||||
w.set_dir(dir);
|
||||
w.set_msize(vals::Size::BITS8);
|
||||
w.set_psize(vals::Size::BITS8);
|
||||
if incr_mem {
|
||||
w.set_minc(vals::Inc::INCREMENTED);
|
||||
} else {
|
||||
w.set_minc(vals::Inc::FIXED);
|
||||
}
|
||||
w.set_pinc(vals::Inc::FIXED);
|
||||
w.set_teie(true);
|
||||
w.set_tcie(true);
|
||||
#[cfg(dma_v1)]
|
||||
w.set_trbuff(true);
|
||||
|
||||
#[cfg(dma_v2)]
|
||||
w.set_chsel(request);
|
||||
|
||||
w.set_en(true);
|
||||
});
|
||||
}
|
||||
|
||||
async move {
|
||||
let res = poll_fn(|cx| {
|
||||
let n = state_number as usize;
|
||||
STATE.ch_wakers[n].register(cx.waker());
|
||||
|
||||
let isr = dma.isr(isrn).read();
|
||||
|
||||
// TODO handle error
|
||||
assert!(!isr.teif(isrbit));
|
||||
|
||||
if isr.tcif(isrbit) {
|
||||
Poll::Ready(())
|
||||
} else {
|
||||
Poll::Pending
|
||||
}
|
||||
})
|
||||
.await;
|
||||
|
||||
drop(on_drop)
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! dma_num {
|
||||
(DMA1) => {
|
||||
0
|
||||
@ -170,88 +83,80 @@ pub(crate) unsafe fn init() {
|
||||
|
||||
pac::dma_channels! {
|
||||
($channel_peri:ident, $dma_peri:ident, dma, $channel_num:expr, $dmamux:tt) => {
|
||||
impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {}
|
||||
impl Channel for crate::peripherals::$channel_peri
|
||||
{
|
||||
type ReadFuture<'a> = impl Future<Output = ()> + 'a;
|
||||
type WriteFuture<'a> = impl Future<Output = ()> + 'a;
|
||||
|
||||
fn read<'a>(
|
||||
&'a mut self,
|
||||
request: Request,
|
||||
src: *mut u8,
|
||||
buf: &'a mut [u8],
|
||||
) -> Self::ReadFuture<'a> {
|
||||
unsafe {
|
||||
do_transfer(
|
||||
crate::pac::$dma_peri,
|
||||
$channel_num,
|
||||
(dma_num!($dma_peri) * 8) + $channel_num,
|
||||
request,
|
||||
vals::Dir::PERIPHERALTOMEMORY,
|
||||
src,
|
||||
buf.as_mut_ptr(),
|
||||
buf.len(),
|
||||
true,
|
||||
#[cfg(dmamux)]
|
||||
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
|
||||
#[cfg(dmamux)]
|
||||
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
|
||||
)
|
||||
}
|
||||
impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {
|
||||
unsafe fn start_write<W: Word>(&mut self, request: Request, buf: &[W], reg_addr: *mut W) {
|
||||
low_level_api::start_transfer(
|
||||
pac::$dma_peri,
|
||||
$channel_num,
|
||||
request,
|
||||
vals::Dir::MEMORYTOPERIPHERAL,
|
||||
reg_addr as *const u32,
|
||||
buf.as_ptr() as *mut u32,
|
||||
buf.len(),
|
||||
true,
|
||||
vals::Size::from(W::bits()),
|
||||
#[cfg(dmamux)]
|
||||
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
|
||||
#[cfg(dmamux)]
|
||||
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
|
||||
)
|
||||
}
|
||||
|
||||
fn write<'a>(
|
||||
&'a mut self,
|
||||
request: Request,
|
||||
buf: &'a [u8],
|
||||
dst: *mut u8,
|
||||
) -> Self::WriteFuture<'a> {
|
||||
unsafe {
|
||||
do_transfer(
|
||||
crate::pac::$dma_peri,
|
||||
$channel_num,
|
||||
(dma_num!($dma_peri) * 8) + $channel_num,
|
||||
request,
|
||||
vals::Dir::MEMORYTOPERIPHERAL,
|
||||
dst,
|
||||
buf.as_ptr() as *mut u8,
|
||||
buf.len(),
|
||||
true,
|
||||
#[cfg(dmamux)]
|
||||
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
|
||||
#[cfg(dmamux)]
|
||||
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
|
||||
)
|
||||
}
|
||||
unsafe fn start_write_repeated<W: Word>(&mut self, request: Request, repeated: W, count: usize, reg_addr: *mut W) {
|
||||
let buf = [repeated];
|
||||
low_level_api::start_transfer(
|
||||
pac::$dma_peri,
|
||||
$channel_num,
|
||||
request,
|
||||
vals::Dir::MEMORYTOPERIPHERAL,
|
||||
reg_addr as *const u32,
|
||||
buf.as_ptr() as *mut u32,
|
||||
count,
|
||||
false,
|
||||
vals::Size::from(W::bits()),
|
||||
#[cfg(dmamux)]
|
||||
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
|
||||
#[cfg(dmamux)]
|
||||
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
|
||||
)
|
||||
}
|
||||
|
||||
fn write_x<'a>(
|
||||
&'a mut self,
|
||||
request: Request,
|
||||
word: &u8,
|
||||
num: usize,
|
||||
dst: *mut u8,
|
||||
) -> Self::WriteFuture<'a> {
|
||||
unsafe {
|
||||
do_transfer(
|
||||
crate::pac::$dma_peri,
|
||||
$channel_num,
|
||||
(dma_num!($dma_peri) * 8) + $channel_num,
|
||||
request,
|
||||
vals::Dir::MEMORYTOPERIPHERAL,
|
||||
dst,
|
||||
word as *const u8 as *mut u8,
|
||||
num,
|
||||
false,
|
||||
#[cfg(dmamux)]
|
||||
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
|
||||
#[cfg(dmamux)]
|
||||
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
|
||||
)
|
||||
}
|
||||
unsafe fn start_read<W: Word>(&mut self, request: Request, reg_addr: *mut W, buf: &mut [W]) {
|
||||
low_level_api::start_transfer(
|
||||
pac::$dma_peri,
|
||||
$channel_num,
|
||||
request,
|
||||
vals::Dir::PERIPHERALTOMEMORY,
|
||||
reg_addr as *const u32,
|
||||
buf.as_ptr() as *mut u32,
|
||||
buf.len(),
|
||||
true,
|
||||
vals::Size::from(W::bits()),
|
||||
#[cfg(dmamux)]
|
||||
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
|
||||
#[cfg(dmamux)]
|
||||
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
|
||||
);
|
||||
}
|
||||
|
||||
fn request_stop(&mut self) {
|
||||
unsafe {low_level_api::request_stop(pac::$dma_peri, $channel_num);}
|
||||
}
|
||||
|
||||
fn is_running(&self) -> bool {
|
||||
unsafe {low_level_api::is_running(pac::$dma_peri, $channel_num)}
|
||||
}
|
||||
|
||||
fn remaining_transfers(&mut self) -> u16 {
|
||||
unsafe {low_level_api::get_remaining_transfers(pac::$dma_peri, $channel_num)}
|
||||
}
|
||||
|
||||
fn set_waker(&mut self, waker: &Waker) {
|
||||
unsafe {low_level_api::set_waker(dma_num!($dma_peri) * 8 + $channel_num, waker )}
|
||||
}
|
||||
}
|
||||
|
||||
impl crate::dma::Channel for crate::peripherals::$channel_peri { }
|
||||
};
|
||||
}
|
||||
|
||||
@ -263,3 +168,102 @@ pac::interrupts! {
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
mod low_level_api {
|
||||
use super::*;
|
||||
|
||||
pub unsafe fn start_transfer(
|
||||
dma: pac::dma::Dma,
|
||||
channel_number: u8,
|
||||
request: Request,
|
||||
dir: vals::Dir,
|
||||
peri_addr: *const u32,
|
||||
mem_addr: *mut u32,
|
||||
mem_len: usize,
|
||||
incr_mem: bool,
|
||||
data_size: vals::Size,
|
||||
#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
|
||||
#[cfg(dmamux)] dmamux_ch_num: u8,
|
||||
) {
|
||||
#[cfg(dmamux)]
|
||||
super::super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
|
||||
|
||||
// "Preceding reads and writes cannot be moved past subsequent writes."
|
||||
fence(Ordering::SeqCst);
|
||||
|
||||
reset_status(dma, channel_number);
|
||||
|
||||
let ch = dma.st(channel_number as _);
|
||||
ch.par().write_value(peri_addr as u32);
|
||||
ch.m0ar().write_value(mem_addr as u32);
|
||||
ch.ndtr().write_value(regs::Ndtr(mem_len as _));
|
||||
ch.cr().write(|w| {
|
||||
w.set_dir(dir);
|
||||
w.set_msize(data_size);
|
||||
w.set_psize(data_size);
|
||||
w.set_pl(vals::Pl::VERYHIGH);
|
||||
if incr_mem {
|
||||
w.set_minc(vals::Inc::INCREMENTED);
|
||||
} else {
|
||||
w.set_minc(vals::Inc::FIXED);
|
||||
}
|
||||
w.set_pinc(vals::Inc::FIXED);
|
||||
w.set_teie(true);
|
||||
w.set_tcie(true);
|
||||
#[cfg(dma_v1)]
|
||||
w.set_trbuff(true);
|
||||
|
||||
#[cfg(dma_v2)]
|
||||
w.set_chsel(request);
|
||||
|
||||
w.set_en(true);
|
||||
});
|
||||
}
|
||||
|
||||
/// Stops the DMA channel.
|
||||
pub unsafe fn request_stop(dma: pac::dma::Dma, channel_number: u8) {
|
||||
// get a handle on the channel itself
|
||||
let ch = dma.st(channel_number as _);
|
||||
|
||||
// Disable the channel. Keep the IEs enabled so the irqs still fire.
|
||||
ch.cr().write(|w| {
|
||||
w.set_teie(true);
|
||||
w.set_tcie(true);
|
||||
});
|
||||
|
||||
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
|
||||
fence(Ordering::SeqCst);
|
||||
}
|
||||
|
||||
/// Gets the running status of the channel
|
||||
pub unsafe fn is_running(dma: pac::dma::Dma, ch: u8) -> bool {
|
||||
// get a handle on the channel itself
|
||||
let ch = dma.st(ch as _);
|
||||
// Get whether it's enabled (running)
|
||||
ch.cr().read().en()
|
||||
}
|
||||
|
||||
/// Gets the total remaining transfers for the channel
|
||||
/// Note: this will be zero for transfers that completed without cancellation.
|
||||
pub unsafe fn get_remaining_transfers(dma: pac::dma::Dma, ch: u8) -> u16 {
|
||||
// get a handle on the channel itself
|
||||
let ch = dma.st(ch as _);
|
||||
// read the remaining transfer count. If this is zero, the transfer completed fully.
|
||||
ch.ndtr().read().ndt()
|
||||
}
|
||||
|
||||
/// Sets the waker for the specified DMA channel
|
||||
pub unsafe fn set_waker(state_number: usize, waker: &Waker) {
|
||||
STATE.ch_wakers[state_number].register(waker);
|
||||
}
|
||||
|
||||
pub unsafe fn reset_status(dma: pac::dma::Dma, channel_number: u8) {
|
||||
let isrn = channel_number as usize / 4;
|
||||
let isrbit = channel_number as usize % 4;
|
||||
|
||||
dma.ifcr(isrn).write(|w| {
|
||||
w.set_tcif(isrbit, true);
|
||||
w.set_teif(isrbit, true);
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
@ -9,7 +9,18 @@ mod dmamux;
|
||||
pub use dmamux::*;
|
||||
|
||||
use core::future::Future;
|
||||
use core::marker::PhantomData;
|
||||
use core::pin::Pin;
|
||||
use core::task::Waker;
|
||||
use core::task::{Context, Poll};
|
||||
use embassy::util::Unborrow;
|
||||
use embassy_hal_common::unborrow;
|
||||
|
||||
#[cfg(feature = "unstable-pac")]
|
||||
pub use transfers::*;
|
||||
|
||||
#[cfg(not(feature = "unstable-pac"))]
|
||||
pub(crate) use transfers::*;
|
||||
|
||||
#[cfg(any(bdma_v2, dma_v2, dmamux))]
|
||||
pub type Request = u8;
|
||||
@ -17,40 +28,179 @@ pub type Request = u8;
|
||||
pub type Request = ();
|
||||
|
||||
pub(crate) mod sealed {
|
||||
pub trait Channel {}
|
||||
use super::*;
|
||||
|
||||
pub trait Word {}
|
||||
|
||||
pub trait Channel {
|
||||
/// Starts this channel for writing a stream of words.
|
||||
///
|
||||
/// Safety:
|
||||
/// - `buf` must be alive for the entire duration of the DMA transfer.
|
||||
/// - `reg_addr` must be a valid peripheral register address to write to.
|
||||
unsafe fn start_write<W: super::Word>(
|
||||
&mut self,
|
||||
request: Request,
|
||||
buf: &[W],
|
||||
reg_addr: *mut W,
|
||||
);
|
||||
|
||||
/// Starts this channel for writing a word repeatedly.
|
||||
///
|
||||
/// Safety:
|
||||
/// - `reg_addr` must be a valid peripheral register address to write to.
|
||||
unsafe fn start_write_repeated<W: super::Word>(
|
||||
&mut self,
|
||||
request: Request,
|
||||
repeated: W,
|
||||
count: usize,
|
||||
reg_addr: *mut W,
|
||||
);
|
||||
|
||||
/// Starts this channel for reading a stream of words.
|
||||
///
|
||||
/// Safety:
|
||||
/// - `buf` must be alive for the entire duration of the DMA transfer.
|
||||
/// - `reg_addr` must be a valid peripheral register address to write to.
|
||||
unsafe fn start_read<W: super::Word>(
|
||||
&mut self,
|
||||
request: Request,
|
||||
reg_addr: *mut W,
|
||||
buf: &mut [W],
|
||||
);
|
||||
|
||||
/// Requests the channel to stop.
|
||||
/// NOTE: The channel does not immediately stop, you have to wait
|
||||
/// for `is_running() = false`.
|
||||
fn request_stop(&mut self);
|
||||
|
||||
/// Returns whether this channel is running or stopped.
|
||||
///
|
||||
/// The channel stops running when it either completes or is manually stopped.
|
||||
fn is_running(&self) -> bool;
|
||||
|
||||
/// Returns the total number of remaining transfers.
|
||||
fn remaining_transfers(&mut self) -> u16;
|
||||
|
||||
/// Sets the waker that is called when this channel stops (either completed or manually stopped)
|
||||
fn set_waker(&mut self, waker: &Waker);
|
||||
}
|
||||
}
|
||||
|
||||
pub trait Channel: sealed::Channel {
|
||||
type ReadFuture<'a>: Future<Output = ()> + 'a
|
||||
where
|
||||
Self: 'a;
|
||||
|
||||
type WriteFuture<'a>: Future<Output = ()> + 'a
|
||||
where
|
||||
Self: 'a;
|
||||
|
||||
fn read<'a>(
|
||||
&'a mut self,
|
||||
request: Request,
|
||||
src: *mut u8,
|
||||
buf: &'a mut [u8],
|
||||
) -> Self::ReadFuture<'a>;
|
||||
|
||||
fn write<'a>(
|
||||
&'a mut self,
|
||||
request: Request,
|
||||
buf: &'a [u8],
|
||||
dst: *mut u8,
|
||||
) -> Self::WriteFuture<'a>;
|
||||
|
||||
fn write_x<'a>(
|
||||
&'a mut self,
|
||||
request: Request,
|
||||
word: &u8,
|
||||
num: usize,
|
||||
dst: *mut u8,
|
||||
) -> Self::WriteFuture<'a>;
|
||||
pub enum WordSize {
|
||||
OneByte,
|
||||
TwoBytes,
|
||||
FourBytes,
|
||||
}
|
||||
pub trait Word: sealed::Word {
|
||||
fn bits() -> WordSize;
|
||||
}
|
||||
|
||||
impl sealed::Word for u8 {}
|
||||
impl Word for u8 {
|
||||
fn bits() -> WordSize {
|
||||
WordSize::OneByte
|
||||
}
|
||||
}
|
||||
|
||||
impl sealed::Word for u16 {}
|
||||
impl Word for u16 {
|
||||
fn bits() -> WordSize {
|
||||
WordSize::TwoBytes
|
||||
}
|
||||
}
|
||||
|
||||
impl sealed::Word for u32 {}
|
||||
impl Word for u32 {
|
||||
fn bits() -> WordSize {
|
||||
WordSize::FourBytes
|
||||
}
|
||||
}
|
||||
|
||||
mod transfers {
|
||||
use super::*;
|
||||
|
||||
#[allow(unused)]
|
||||
pub fn read<'a, W: Word>(
|
||||
channel: impl Unborrow<Target = impl Channel> + 'a,
|
||||
request: Request,
|
||||
reg_addr: *mut W,
|
||||
buf: &'a mut [W],
|
||||
) -> impl Future<Output = ()> + 'a {
|
||||
assert!(buf.len() <= 0xFFFF);
|
||||
unborrow!(channel);
|
||||
|
||||
unsafe { channel.start_read::<W>(request, reg_addr, buf) };
|
||||
|
||||
Transfer {
|
||||
channel,
|
||||
_phantom: PhantomData,
|
||||
}
|
||||
}
|
||||
|
||||
#[allow(unused)]
|
||||
pub fn write<'a, W: Word>(
|
||||
channel: impl Unborrow<Target = impl Channel> + 'a,
|
||||
request: Request,
|
||||
buf: &'a [W],
|
||||
reg_addr: *mut W,
|
||||
) -> impl Future<Output = ()> + 'a {
|
||||
assert!(buf.len() <= 0xFFFF);
|
||||
unborrow!(channel);
|
||||
|
||||
unsafe { channel.start_write::<W>(request, buf, reg_addr) };
|
||||
|
||||
Transfer {
|
||||
channel,
|
||||
_phantom: PhantomData,
|
||||
}
|
||||
}
|
||||
|
||||
#[allow(unused)]
|
||||
pub fn write_repeated<'a, W: Word>(
|
||||
channel: impl Unborrow<Target = impl Channel> + 'a,
|
||||
request: Request,
|
||||
repeated: W,
|
||||
count: usize,
|
||||
reg_addr: *mut W,
|
||||
) -> impl Future<Output = ()> + 'a {
|
||||
unborrow!(channel);
|
||||
|
||||
unsafe { channel.start_write_repeated::<W>(request, repeated, count, reg_addr) };
|
||||
|
||||
Transfer {
|
||||
channel,
|
||||
_phantom: PhantomData,
|
||||
}
|
||||
}
|
||||
|
||||
struct Transfer<'a, C: Channel> {
|
||||
channel: C,
|
||||
_phantom: PhantomData<&'a mut C>,
|
||||
}
|
||||
|
||||
impl<'a, C: Channel> Drop for Transfer<'a, C> {
|
||||
fn drop(&mut self) {
|
||||
self.channel.request_stop();
|
||||
while self.channel.is_running() {}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a, C: Channel> Unpin for Transfer<'a, C> {}
|
||||
impl<'a, C: Channel> Future for Transfer<'a, C> {
|
||||
type Output = ();
|
||||
fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
|
||||
self.channel.set_waker(cx.waker());
|
||||
if self.channel.is_running() {
|
||||
Poll::Pending
|
||||
} else {
|
||||
Poll::Ready(())
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub trait Channel: sealed::Channel + Unborrow<Target = Self> + 'static {}
|
||||
|
||||
pub struct NoDma;
|
||||
|
||||
|
||||
@ -418,7 +418,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
let dst = regs.txdr().ptr() as *mut u8;
|
||||
|
||||
let ch = &mut self.tx_dma;
|
||||
ch.write(ch.request(), bytes, dst)
|
||||
let request = ch.request();
|
||||
crate::dma::write(ch, request, bytes, dst)
|
||||
};
|
||||
|
||||
let state_number = T::state_number();
|
||||
@ -510,7 +511,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
let src = regs.rxdr().ptr() as *mut u8;
|
||||
|
||||
let ch = &mut self.rx_dma;
|
||||
ch.read(ch.request(), src, buffer)
|
||||
let request = ch.request();
|
||||
crate::dma::read(ch, request, src, buffer)
|
||||
};
|
||||
|
||||
let state_number = T::state_number();
|
||||
|
||||
@ -20,7 +20,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
|
||||
|
||||
let request = self.txdma.request();
|
||||
let dst = T::regs().tx_ptr();
|
||||
let f = self.txdma.write(request, write, dst);
|
||||
let f = crate::dma::write(&mut self.txdma, request, write, dst);
|
||||
|
||||
unsafe {
|
||||
T::regs().cr2().modify(|reg| {
|
||||
@ -54,14 +54,18 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
|
||||
|
||||
let rx_request = self.rxdma.request();
|
||||
let rx_src = T::regs().rx_ptr();
|
||||
let rx_f = self.rxdma.read(rx_request, rx_src, read);
|
||||
let rx_f = crate::dma::read(&mut self.rxdma, rx_request, rx_src, read);
|
||||
|
||||
let tx_request = self.txdma.request();
|
||||
let tx_dst = T::regs().tx_ptr();
|
||||
let clock_byte = 0x00;
|
||||
let tx_f = self
|
||||
.txdma
|
||||
.write_x(tx_request, &clock_byte, clock_byte_count, tx_dst);
|
||||
let clock_byte = 0x00u8;
|
||||
let tx_f = crate::dma::write_repeated(
|
||||
&mut self.txdma,
|
||||
tx_request,
|
||||
clock_byte,
|
||||
clock_byte_count,
|
||||
tx_dst,
|
||||
);
|
||||
|
||||
unsafe {
|
||||
T::regs().cr2().modify(|reg| {
|
||||
@ -110,13 +114,16 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
|
||||
|
||||
let rx_request = self.rxdma.request();
|
||||
let rx_src = T::regs().rx_ptr();
|
||||
let rx_f = self
|
||||
.rxdma
|
||||
.read(rx_request, rx_src, &mut read[0..write.len()]);
|
||||
let rx_f = crate::dma::read(
|
||||
&mut self.rxdma,
|
||||
rx_request,
|
||||
rx_src,
|
||||
&mut read[0..write.len()],
|
||||
);
|
||||
|
||||
let tx_request = self.txdma.request();
|
||||
let tx_dst = T::regs().tx_ptr();
|
||||
let tx_f = self.txdma.write(tx_request, write, tx_dst);
|
||||
let tx_f = crate::dma::write(&mut self.txdma, tx_request, write, tx_dst);
|
||||
|
||||
unsafe {
|
||||
T::regs().cr2().modify(|reg| {
|
||||
|
||||
@ -24,7 +24,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
|
||||
|
||||
let request = self.txdma.request();
|
||||
let dst = T::regs().tx_ptr();
|
||||
let f = self.txdma.write(request, write, dst);
|
||||
let f = crate::dma::write(&mut self.txdma, request, write, dst);
|
||||
|
||||
unsafe {
|
||||
T::regs().cr2().modify(|reg| {
|
||||
@ -67,14 +67,18 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
|
||||
|
||||
let rx_request = self.rxdma.request();
|
||||
let rx_src = T::regs().rx_ptr();
|
||||
let rx_f = self.rxdma.read(rx_request, rx_src, read);
|
||||
let rx_f = crate::dma::read(&mut self.rxdma, rx_request, rx_src, read);
|
||||
|
||||
let tx_request = self.txdma.request();
|
||||
let tx_dst = T::regs().tx_ptr();
|
||||
let clock_byte = 0x00;
|
||||
let tx_f = self
|
||||
.txdma
|
||||
.write_x(tx_request, &clock_byte, clock_byte_count, tx_dst);
|
||||
let clock_byte = 0x00u8;
|
||||
let tx_f = crate::dma::write_repeated(
|
||||
&mut self.txdma,
|
||||
tx_request,
|
||||
clock_byte,
|
||||
clock_byte_count,
|
||||
tx_dst,
|
||||
);
|
||||
|
||||
unsafe {
|
||||
T::regs().cr2().modify(|reg| {
|
||||
@ -128,13 +132,16 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
|
||||
|
||||
let rx_request = self.rxdma.request();
|
||||
let rx_src = T::regs().rx_ptr();
|
||||
let rx_f = self
|
||||
.rxdma
|
||||
.read(rx_request, rx_src, &mut read[0..write.len()]);
|
||||
let rx_f = crate::dma::read(
|
||||
&mut self.rxdma,
|
||||
rx_request,
|
||||
rx_src,
|
||||
&mut read[0..write.len()],
|
||||
);
|
||||
|
||||
let tx_request = self.txdma.request();
|
||||
let tx_dst = T::regs().tx_ptr();
|
||||
let tx_f = self.txdma.write(tx_request, write, tx_dst);
|
||||
let tx_f = crate::dma::write(&mut self.txdma, tx_request, write, tx_dst);
|
||||
|
||||
unsafe {
|
||||
T::regs().cr2().modify(|reg| {
|
||||
|
||||
@ -24,7 +24,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
|
||||
|
||||
let request = self.txdma.request();
|
||||
let dst = T::regs().tx_ptr();
|
||||
let f = self.txdma.write(request, write, dst);
|
||||
let f = crate::dma::write(&mut self.txdma, request, write, dst);
|
||||
|
||||
unsafe {
|
||||
T::regs().cfg1().modify(|reg| {
|
||||
@ -70,14 +70,18 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
|
||||
|
||||
let rx_request = self.rxdma.request();
|
||||
let rx_src = T::regs().rx_ptr();
|
||||
let rx_f = self.rxdma.read(rx_request, rx_src, read);
|
||||
let rx_f = crate::dma::read(&mut self.rxdma, rx_request, rx_src, read);
|
||||
|
||||
let tx_request = self.txdma.request();
|
||||
let tx_dst = T::regs().tx_ptr();
|
||||
let clock_byte = 0x00;
|
||||
let tx_f = self
|
||||
.txdma
|
||||
.write_x(tx_request, &clock_byte, clock_byte_count, tx_dst);
|
||||
let clock_byte = 0x00u8;
|
||||
let tx_f = crate::dma::write_repeated(
|
||||
&mut self.txdma,
|
||||
tx_request,
|
||||
clock_byte,
|
||||
clock_byte_count,
|
||||
tx_dst,
|
||||
);
|
||||
|
||||
unsafe {
|
||||
T::regs().cfg1().modify(|reg| {
|
||||
@ -132,13 +136,16 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
|
||||
|
||||
let rx_request = self.rxdma.request();
|
||||
let rx_src = T::regs().rx_ptr();
|
||||
let rx_f = self
|
||||
.rxdma
|
||||
.read(rx_request, rx_src, &mut read[0..write.len()]);
|
||||
let rx_f = crate::dma::read(
|
||||
&mut self.rxdma,
|
||||
rx_request,
|
||||
rx_src,
|
||||
&mut read[0..write.len()],
|
||||
);
|
||||
|
||||
let tx_request = self.txdma.request();
|
||||
let tx_dst = T::regs().tx_ptr();
|
||||
let tx_f = self.txdma.write(tx_request, write, tx_dst);
|
||||
let tx_f = crate::dma::write(&mut self.txdma, tx_request, write, tx_dst);
|
||||
|
||||
unsafe {
|
||||
T::regs().cfg1().modify(|reg| {
|
||||
|
||||
@ -70,6 +70,7 @@ impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
TxDma: crate::usart::TxDma<T>,
|
||||
{
|
||||
let ch = &mut self.tx_dma;
|
||||
let request = ch.request();
|
||||
unsafe {
|
||||
self.inner.regs().cr3().modify(|reg| {
|
||||
reg.set_dmat(true);
|
||||
@ -77,7 +78,7 @@ impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
}
|
||||
let r = self.inner.regs();
|
||||
let dst = r.dr().ptr() as *mut u8;
|
||||
ch.write(ch.request(), buffer, dst).await;
|
||||
crate::dma::write(ch, request, buffer, dst).await;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
@ -86,6 +87,7 @@ impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
RxDma: crate::usart::RxDma<T>,
|
||||
{
|
||||
let ch = &mut self.rx_dma;
|
||||
let request = ch.request();
|
||||
unsafe {
|
||||
self.inner.regs().cr3().modify(|reg| {
|
||||
reg.set_dmar(true);
|
||||
@ -93,7 +95,7 @@ impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
}
|
||||
let r = self.inner.regs();
|
||||
let src = r.dr().ptr() as *mut u8;
|
||||
ch.read(ch.request(), src, buffer).await;
|
||||
crate::dma::read(ch, request, src, buffer).await;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
|
||||
@ -80,6 +80,7 @@ impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
TxDma: crate::usart::TxDma<T>,
|
||||
{
|
||||
let ch = &mut self.tx_dma;
|
||||
let request = ch.request();
|
||||
unsafe {
|
||||
self.inner.regs().cr3().modify(|reg| {
|
||||
reg.set_dmat(true);
|
||||
@ -87,7 +88,7 @@ impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
}
|
||||
let r = self.inner.regs();
|
||||
let dst = r.tdr().ptr() as *mut u8;
|
||||
ch.write(ch.request(), buffer, dst).await;
|
||||
crate::dma::write(ch, request, buffer, dst).await;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
@ -96,6 +97,7 @@ impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
RxDma: crate::usart::RxDma<T>,
|
||||
{
|
||||
let ch = &mut self.rx_dma;
|
||||
let request = ch.request();
|
||||
unsafe {
|
||||
self.inner.regs().cr3().modify(|reg| {
|
||||
reg.set_dmar(true);
|
||||
@ -103,7 +105,8 @@ impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
}
|
||||
let r = self.inner.regs();
|
||||
let src = r.rdr().ptr() as *mut u8;
|
||||
ch.read(ch.request(), src, buffer).await;
|
||||
|
||||
crate::dma::read(ch, request, src, buffer).await;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user