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Remove wrong modulo

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This commit is contained in:
Joël Schulz-Andres 2024-05-24 16:54:04 +02:00
parent 5cba97821f
commit ac76a713e1
1 changed files with 2 additions and 2 deletions
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4
embassy-stm32/src/gpio.rs
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@ -688,7 +688,7 @@ pub(crate) trait SealedPin {
let crlh = if n < 8 { 0 } else { 1 };
match r.cr(crlh).read().mode(n % 8) {
vals::Mode::INPUT => match r.cr(crlh).read().cnf_in(n % 8) {
vals::CnfIn::PULL => match r.odr().read().odr(n % 8) {
vals::CnfIn::PULL => match r.odr().read().odr(n) {
vals::Odr::LOW => Pull::Down,
vals::Odr::HIGH => Pull::Up,
},
@ -699,7 +699,7 @@ pub(crate) trait SealedPin {
}
#[cfg(gpio_v2)]
{
match r.pupdr().read().pupdr(n % 8) {
match r.pupdr().read().pupdr(n) {
vals::Pupdr::FLOATING => Pull::None,
vals::Pupdr::PULLDOWN => Pull::Down,
vals::Pupdr::PULLUP => Pull::Up,