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https://github.com/embassy-rs/embassy.git
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Merge pull request #1987 from tyler-gilbert/issue-1986-add-sai-receiver-driver
Issue 1986 add sai receiver driver
This commit is contained in:
xoviat
GitHub
commit
a7b1e51650
@ -4,7 +4,7 @@ use embassy_embedded_hal::SetConfig;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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pub use crate::dma::word;
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use crate::dma::{ringbuffer, Channel, ReadableRingBuffer, TransferOptions, WritableRingBuffer};
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use crate::dma::{ringbuffer, Channel, ReadableRingBuffer, Request, TransferOptions, WritableRingBuffer};
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use crate::gpio::sealed::{AFType, Pin as _};
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use crate::gpio::AnyPin;
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use crate::pac::sai::{vals, Sai as Regs};
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@ -48,8 +48,8 @@ pub enum Mode {
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}
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#[derive(Copy, Clone)]
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enum TxRx {
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Transmiter,
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pub enum TxRx {
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Transmitter,
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Receiver,
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}
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@ -57,7 +57,7 @@ impl Mode {
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#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
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const fn mode(&self, tx_rx: TxRx) -> vals::Mode {
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match tx_rx {
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TxRx::Transmiter => match self {
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TxRx::Transmitter => match self {
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Mode::Master => vals::Mode::MASTERTX,
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Mode::Slave => vals::Mode::SLAVETX,
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},
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@ -206,12 +206,13 @@ impl Protocol {
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}
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}
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#[derive(Copy, Clone)]
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#[derive(Copy, Clone, PartialEq)]
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pub enum SyncEnable {
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Asynchronous,
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/// Syncs with the other A/B sub-block within the SAI unit
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Internal,
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/// Syncs with a sub-block in the other SAI unit - use set_sync_output() and set_sync_input()
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#[cfg(any(sai_v4))]
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External,
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}
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@ -221,6 +222,7 @@ impl SyncEnable {
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match self {
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SyncEnable::Asynchronous => vals::Syncen::ASYNCHRONOUS,
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SyncEnable::Internal => vals::Syncen::INTERNAL,
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#[cfg(any(sai_v4))]
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SyncEnable::External => vals::Syncen::EXTERNAL,
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}
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}
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@ -425,6 +427,7 @@ impl MasterClockDivider {
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#[derive(Copy, Clone)]
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pub struct Config {
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pub mode: Mode,
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pub tx_rx: TxRx,
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pub sync_enable: SyncEnable,
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pub is_sync_output: bool,
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pub protocol: Protocol,
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@ -455,6 +458,7 @@ impl Default for Config {
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fn default() -> Self {
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Self {
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mode: Mode::Master,
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tx_rx: TxRx::Transmitter,
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is_sync_output: false,
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sync_enable: SyncEnable::Asynchronous,
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protocol: Protocol::Free,
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@ -498,42 +502,127 @@ impl Config {
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}
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#[derive(Copy, Clone)]
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pub enum SubBlock {
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enum WhichSubBlock {
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A = 0,
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B = 1,
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}
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enum RingBuffer<'d, C: Channel, W: word::Word> {
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Writable(WritableRingBuffer<'d, C, W>),
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#[allow(dead_code)] // remove this after implementing new_* functions for receiver
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Readable(ReadableRingBuffer<'d, C, W>),
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}
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#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
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fn wdr<W: word::Word>(w: crate::pac::sai::Sai, sub_block: SubBlock) -> *mut W {
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fn dr<W: word::Word>(w: crate::pac::sai::Sai, sub_block: WhichSubBlock) -> *mut W {
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let ch = w.ch(sub_block as usize);
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ch.dr().as_ptr() as _
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}
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pub struct Sai<'d, T: Instance, C: Channel, W: word::Word> {
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pub struct SubBlock<'d, T: Instance, C: Channel, W: word::Word> {
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_peri: PeripheralRef<'d, T>,
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sd: Option<PeripheralRef<'d, AnyPin>>,
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fs: Option<PeripheralRef<'d, AnyPin>>,
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sck: Option<PeripheralRef<'d, AnyPin>>,
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mclk: Option<PeripheralRef<'d, AnyPin>>,
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ring_buffer: RingBuffer<'d, C, W>,
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sub_block: SubBlock,
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sub_block: WhichSubBlock,
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}
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impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
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fn get_transmitter_af_types(mode: Mode) -> (AFType, AFType) {
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pub struct SubBlockA {}
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pub struct SubBlockB {}
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pub struct Sai<'d, T: Instance> {
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_peri: PeripheralRef<'d, T>,
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sub_block_a_peri: Option<PeripheralRef<'d, T>>,
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sub_block_b_peri: Option<PeripheralRef<'d, T>>,
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}
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// return the type for (sd, sck)
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fn get_af_types(mode: Mode, tx_rx: TxRx) -> (AFType, AFType) {
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(
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//sd is defined by tx/rx mode
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match tx_rx {
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TxRx::Transmitter => AFType::OutputPushPull,
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TxRx::Receiver => AFType::Input,
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},
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//clocks (mclk, sck and fs) are defined by master/slave
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match mode {
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Mode::Master => (AFType::OutputPushPull, AFType::OutputPushPull),
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Mode::Slave => (AFType::OutputPushPull, AFType::Input),
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Mode::Master => AFType::OutputPushPull,
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Mode::Slave => AFType::Input,
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},
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)
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}
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fn get_ring_buffer<'d, T: Instance, C: Channel, W: word::Word>(
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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request: Request,
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sub_block: WhichSubBlock,
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tx_rx: TxRx,
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) -> RingBuffer<'d, C, W> {
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let opts = TransferOptions {
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half_transfer_ir: true,
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//the new_write() and new_read() always use circular mode
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..Default::default()
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};
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match tx_rx {
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TxRx::Transmitter => RingBuffer::Writable(unsafe {
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WritableRingBuffer::new_write(dma, request, dr(T::REGS, sub_block), dma_buf, opts)
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}),
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TxRx::Receiver => RingBuffer::Readable(unsafe {
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ReadableRingBuffer::new_read(dma, request, dr(T::REGS, sub_block), dma_buf, opts)
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}),
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}
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}
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pub fn new_asynchronous_transmitter_with_mclk_a(
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impl<'d, T: Instance> Sai<'d, T> {
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pub fn new(peri: impl Peripheral<P = T> + 'd) -> Self {
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T::enable();
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T::reset();
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Self {
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_peri: unsafe { peri.clone_unchecked().into_ref() },
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sub_block_a_peri: Some(unsafe { peri.clone_unchecked().into_ref() }),
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sub_block_b_peri: Some(peri.into_ref()),
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}
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}
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pub fn take_sub_block_a(self: &mut Self) -> Option<PeripheralRef<'d, T>> {
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if self.sub_block_a_peri.is_some() {
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self.sub_block_a_peri.take()
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} else {
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None
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}
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}
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pub fn take_sub_block_b(self: &mut Self) -> Option<PeripheralRef<'d, T>> {
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if self.sub_block_b_peri.is_some() {
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self.sub_block_b_peri.take()
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} else {
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None
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}
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}
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}
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fn update_synchronous_config(config: &mut Config) {
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config.mode = Mode::Slave;
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config.is_sync_output = false;
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#[cfg(any(sai_v1, sai_v2, sai_v3))]
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{
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config.sync_enable = SyncEnable::Internal;
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}
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#[cfg(any(sai_v4))]
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{
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//this must either be Internal or External
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//The asynchronous sub-block on the same SAI needs to enable is_sync_output
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assert!(config.sync_enable != SyncEnable::Asynchronous);
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}
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}
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impl SubBlockA {
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pub fn new_asynchronous_with_mclk<'d, T: Instance, C: Channel, W: word::Word>(
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckAPin<T>> + 'd,
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sd: impl Peripheral<P = impl SdAPin<T>> + 'd,
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@ -542,23 +631,25 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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mut config: Config,
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) -> Self
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) -> SubBlock<T, C, W>
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where
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C: Channel + DmaA<T>,
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{
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into_ref!(mclk);
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mclk.set_as_af(mclk.af_num(), AFType::OutputPushPull);
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let (_sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
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mclk.set_as_af(mclk.af_num(), ck_af_type);
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mclk.set_speed(crate::gpio::Speed::VeryHigh);
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if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
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config.master_clock_divider = MasterClockDivider::Div1;
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}
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Self::new_asynchronous_transmitter_a(peri, sck, sd, fs, dma, dma_buf, config)
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Self::new_asynchronous(peri, sck, sd, fs, dma, dma_buf, config)
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}
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pub fn new_asynchronous_transmitter_a(
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pub fn new_asynchronous<'d, T: Instance, C: Channel, W: word::Word>(
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckAPin<T>> + 'd,
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sd: impl Peripheral<P = impl SdAPin<T>> + 'd,
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@ -566,13 +657,13 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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config: Config,
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) -> Self
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) -> SubBlock<T, C, W>
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where
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C: Channel + DmaA<T>,
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{
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into_ref!(peri, dma, sck, sd, fs);
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let (sd_af_type, ck_af_type) = Self::get_transmitter_af_types(config.mode);
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let (sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
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sd.set_as_af(sd.af_num(), sd_af_type);
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sd.set_speed(crate::gpio::Speed::VeryHigh);
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@ -581,30 +672,58 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
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fs.set_as_af(fs.af_num(), ck_af_type);
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fs.set_speed(crate::gpio::Speed::VeryHigh);
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let sub_block = WhichSubBlock::A;
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let request = dma.request();
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let opts = TransferOptions {
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half_transfer_ir: true,
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circular: true,
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..Default::default()
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};
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let sub_block = SubBlock::A;
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Self::new_inner(
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SubBlock::new_inner(
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peri,
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sub_block,
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Some(sck.map_into()),
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None,
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Some(sd.map_into()),
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Some(fs.map_into()),
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RingBuffer::Writable(unsafe {
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WritableRingBuffer::new_write(dma, request, wdr(T::REGS, sub_block), dma_buf, opts)
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}),
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get_ring_buffer::<T, C, W>(dma, dma_buf, request, sub_block, config.tx_rx),
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config,
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)
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}
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pub fn new_asynchronous_transmitter_with_mclk_b(
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pub fn new_synchronous<'d, T: Instance, C: Channel, W: word::Word>(
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peri: impl Peripheral<P = T> + 'd,
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sd: impl Peripheral<P = impl SdAPin<T>> + 'd,
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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mut config: Config,
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) -> SubBlock<T, C, W>
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where
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C: Channel + DmaA<T>,
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{
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update_synchronous_config(&mut config);
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into_ref!(dma, peri, sd);
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let (sd_af_type, _ck_af_type) = get_af_types(config.mode, config.tx_rx);
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sd.set_as_af(sd.af_num(), sd_af_type);
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sd.set_speed(crate::gpio::Speed::VeryHigh);
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let sub_block = WhichSubBlock::A;
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let request = dma.request();
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SubBlock::new_inner(
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peri,
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sub_block,
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None,
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None,
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Some(sd.map_into()),
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None,
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get_ring_buffer::<T, C, W>(dma, dma_buf, request, sub_block, config.tx_rx),
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config,
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)
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}
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}
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impl SubBlockB {
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pub fn new_asynchronous_with_mclk<'d, T: Instance, C: Channel, W: word::Word>(
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckBPin<T>> + 'd,
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sd: impl Peripheral<P = impl SdBPin<T>> + 'd,
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@ -613,23 +732,25 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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mut config: Config,
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) -> Self
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) -> SubBlock<T, C, W>
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where
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C: Channel + DmaB<T>,
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{
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into_ref!(mclk);
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mclk.set_as_af(mclk.af_num(), AFType::OutputPushPull);
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let (_sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
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mclk.set_as_af(mclk.af_num(), ck_af_type);
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mclk.set_speed(crate::gpio::Speed::VeryHigh);
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if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
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config.master_clock_divider = MasterClockDivider::Div1;
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}
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Self::new_asynchronous_transmitter_b(peri, sck, sd, fs, dma, dma_buf, config)
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Self::new_asynchronous(peri, sck, sd, fs, dma, dma_buf, config)
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}
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pub fn new_asynchronous_transmitter_b(
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pub fn new_asynchronous<'d, T: Instance, C: Channel, W: word::Word>(
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckBPin<T>> + 'd,
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sd: impl Peripheral<P = impl SdBPin<T>> + 'd,
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@ -637,13 +758,13 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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config: Config,
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) -> Self
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) -> SubBlock<T, C, W>
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where
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C: Channel + DmaB<T>,
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{
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into_ref!(dma, peri, sck, sd, fs);
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let (sd_af_type, ck_af_type) = Self::get_transmitter_af_types(config.mode);
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let (sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
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sd.set_as_af(sd.af_num(), sd_af_type);
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sd.set_speed(crate::gpio::Speed::VeryHigh);
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@ -653,28 +774,57 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
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fs.set_as_af(fs.af_num(), ck_af_type);
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fs.set_speed(crate::gpio::Speed::VeryHigh);
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let sub_block = WhichSubBlock::B;
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let request = dma.request();
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let opts = TransferOptions {
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half_transfer_ir: true,
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..Default::default()
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};
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let sub_block = SubBlock::B;
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Self::new_inner(
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SubBlock::new_inner(
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peri,
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sub_block,
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Some(sck.map_into()),
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None,
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Some(sd.map_into()),
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Some(fs.map_into()),
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RingBuffer::Writable(unsafe {
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WritableRingBuffer::new_write(dma, request, wdr(T::REGS, sub_block), dma_buf, opts)
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}),
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get_ring_buffer::<T, C, W>(dma, dma_buf, request, sub_block, config.tx_rx),
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config,
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)
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}
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pub fn new_synchronous<'d, T: Instance, C: Channel, W: word::Word>(
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peri: impl Peripheral<P = T> + 'd,
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sd: impl Peripheral<P = impl SdBPin<T>> + 'd,
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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mut config: Config,
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) -> SubBlock<T, C, W>
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where
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C: Channel + DmaB<T>,
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{
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update_synchronous_config(&mut config);
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into_ref!(dma, peri, sd);
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let (sd_af_type, _ck_af_type) = get_af_types(config.mode, config.tx_rx);
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sd.set_as_af(sd.af_num(), sd_af_type);
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sd.set_speed(crate::gpio::Speed::VeryHigh);
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let sub_block = WhichSubBlock::B;
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let request = dma.request();
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SubBlock::new_inner(
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peri,
|
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sub_block,
|
||||
None,
|
||||
None,
|
||||
Some(sd.map_into()),
|
||||
None,
|
||||
get_ring_buffer::<T, C, W>(dma, dma_buf, request, sub_block, config.tx_rx),
|
||||
config,
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, C: Channel, W: word::Word> SubBlock<'d, T, C, W> {
|
||||
pub fn start(self: &mut Self) {
|
||||
match self.ring_buffer {
|
||||
RingBuffer::Writable(ref mut rb) => {
|
||||
@ -695,7 +845,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
|
||||
|
||||
fn new_inner(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
sub_block: SubBlock,
|
||||
sub_block: WhichSubBlock,
|
||||
sck: Option<PeripheralRef<'d, AnyPin>>,
|
||||
mclk: Option<PeripheralRef<'d, AnyPin>>,
|
||||
sd: Option<PeripheralRef<'d, AnyPin>>,
|
||||
@ -704,12 +854,21 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
|
||||
config: Config,
|
||||
) -> Self {
|
||||
T::enable();
|
||||
T::reset();
|
||||
|
||||
// can't reset here because the other sub-block might be in use
|
||||
|
||||
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
|
||||
{
|
||||
let ch = T::REGS.ch(sub_block as usize);
|
||||
ch.cr1().modify(|w| w.set_saien(false));
|
||||
}
|
||||
|
||||
#[cfg(any(sai_v4))]
|
||||
{
|
||||
// Not totally clear from the datasheet if this is right
|
||||
// This is only used if using SyncEnable::External
|
||||
// This is only used if using SyncEnable::External on the other SAI unit
|
||||
// Syncing from SAIX subblock A to subblock B does not require this
|
||||
// Only syncing from SAI1 subblock A/B to SAI2 subblock A/B
|
||||
let value: u8 = if T::REGS.as_ptr() == stm32_metapac::SAI1.as_ptr() {
|
||||
1 //this is SAI1, so sync with SAI2
|
||||
} else {
|
||||
@ -721,8 +880,8 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
|
||||
|
||||
if config.is_sync_output {
|
||||
let syncout: u8 = match sub_block {
|
||||
SubBlock::A => 0b01,
|
||||
SubBlock::B => 0b10,
|
||||
WhichSubBlock::A => 0b01,
|
||||
WhichSubBlock::B => 0b10,
|
||||
};
|
||||
T::REGS.gcr().modify(|w| {
|
||||
w.set_syncout(syncout);
|
||||
@ -735,7 +894,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
|
||||
let ch = T::REGS.ch(sub_block as usize);
|
||||
ch.cr1().modify(|w| {
|
||||
w.set_mode(config.mode.mode(if Self::is_transmitter(&ring_buffer) {
|
||||
TxRx::Transmiter
|
||||
TxRx::Transmitter
|
||||
} else {
|
||||
TxRx::Receiver
|
||||
}));
|
||||
@ -770,7 +929,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
|
||||
w.set_fsoff(config.frame_sync_offset.fsoff());
|
||||
w.set_fspol(config.frame_sync_polarity.fspol());
|
||||
w.set_fsdef(config.frame_sync_definition.fsdef());
|
||||
w.set_fsall(config.frame_sync_active_level_length.0 as u8);
|
||||
w.set_fsall(config.frame_sync_active_level_length.0 as u8 - 1);
|
||||
w.set_frl(config.frame_length - 1);
|
||||
});
|
||||
|
||||
@ -782,6 +941,10 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
|
||||
});
|
||||
|
||||
ch.cr1().modify(|w| w.set_saien(true));
|
||||
|
||||
if ch.cr1().read().saien() == false {
|
||||
panic!("SAI failed to enable. Check that config is valid (frame length, slot count, etc)");
|
||||
}
|
||||
}
|
||||
|
||||
Self {
|
||||
@ -795,6 +958,11 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
|
||||
}
|
||||
}
|
||||
|
||||
pub fn reset() {
|
||||
T::enable();
|
||||
T::reset();
|
||||
}
|
||||
|
||||
pub fn flush(&mut self) {
|
||||
let ch = T::REGS.ch(self.sub_block as usize);
|
||||
ch.cr1().modify(|w| w.set_saien(false));
|
||||
@ -842,7 +1010,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, C: Channel, W: word::Word> Drop for Sai<'d, T, C, W> {
|
||||
impl<'d, T: Instance, C: Channel, W: word::Word> Drop for SubBlock<'d, T, C, W> {
|
||||
fn drop(&mut self) {
|
||||
let ch = T::REGS.ch(self.sub_block as usize);
|
||||
ch.cr1().modify(|w| w.set_saien(false));
|
||||
@ -886,9 +1054,9 @@ foreach_peripheral!(
|
||||
};
|
||||
);
|
||||
|
||||
impl<'d, T: Instance, C: Channel, W: word::Word> SetConfig for Sai<'d, T, C, W> {
|
||||
impl<'d, T: Instance> SetConfig for Sai<'d, T> {
|
||||
type Config = Config;
|
||||
fn set_config(&mut self, config: &Self::Config) {
|
||||
self.reconfigure(*config);
|
||||
fn set_config(&mut self, _config: &Self::Config) {
|
||||
// self.reconfigure(*config);
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user