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Fix txonly/rxonly data pin dir, _from_ram and doc

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This commit is contained in:
Henrik Alsér 2022-11-22 00:55:05 +01:00
parent af34fc4ccc
commit a6d941fac3
1 changed files with 7 additions and 7 deletions
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14
embassy-nrf/src/spis.rs
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@ -78,7 +78,7 @@ impl<'d, T: Instance> Spis<'d, T> {
irq: impl Peripheral<P = T::Interrupt> + 'd, irq: impl Peripheral<P = T::Interrupt> + 'd,
cs: impl Peripheral<P = impl GpioPin> + 'd, cs: impl Peripheral<P = impl GpioPin> + 'd,
sck: impl Peripheral<P = impl GpioPin> + 'd, sck: impl Peripheral<P = impl GpioPin> + 'd,
mosi: impl Peripheral<P = impl GpioPin> + 'd, miso: impl Peripheral<P = impl GpioPin> + 'd,
config: Config, config: Config,
) -> Self { ) -> Self {
into_ref!(cs, sck, mosi); into_ref!(cs, sck, mosi);
@ -87,8 +87,8 @@ impl<'d, T: Instance> Spis<'d, T> {
irq, irq,
cs.map_into(), cs.map_into(),
sck.map_into(), sck.map_into(),
Some(miso.map_into()),
None, None,
Some(mosi.map_into()),
config, config,
) )
} }
@ -98,7 +98,7 @@ impl<'d, T: Instance> Spis<'d, T> {
irq: impl Peripheral<P = T::Interrupt> + 'd, irq: impl Peripheral<P = T::Interrupt> + 'd,
cs: impl Peripheral<P = impl GpioPin> + 'd, cs: impl Peripheral<P = impl GpioPin> + 'd,
sck: impl Peripheral<P = impl GpioPin> + 'd, sck: impl Peripheral<P = impl GpioPin> + 'd,
miso: impl Peripheral<P = impl GpioPin> + 'd, mosi: impl Peripheral<P = impl GpioPin> + 'd,
config: Config, config: Config,
) -> Self { ) -> Self {
into_ref!(cs, sck, miso); into_ref!(cs, sck, miso);
@ -107,8 +107,8 @@ impl<'d, T: Instance> Spis<'d, T> {
irq, irq,
cs.map_into(), cs.map_into(),
sck.map_into(), sck.map_into(),
Some(miso.map_into()),
None, None,
Some(mosi.map_into()),
config, config,
) )
} }
@ -355,7 +355,7 @@ impl<'d, T: Instance> Spis<'d, T> {
} }
} }
/// Reads data from the SPI bus without sending anything. Blocks until the buffer has been filled. /// Reads data from the SPI bus without sending anything. Blocks until `cs` is deasserted.
/// Returns number of bytes read. /// Returns number of bytes read.
pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<usize, Error> { pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<usize, Error> {
self.blocking_inner(data, &[]).map(|n| n.0) self.blocking_inner(data, &[]).map(|n| n.0)
@ -371,7 +371,7 @@ impl<'d, T: Instance> Spis<'d, T> {
/// Same as [`blocking_transfer`](Spis::blocking_transfer) but will fail instead of copying data into RAM. Consult the module level documentation to learn more. /// Same as [`blocking_transfer`](Spis::blocking_transfer) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
/// Returns number of bytes transferred `(n_rx, n_tx)`. /// Returns number of bytes transferred `(n_rx, n_tx)`.
pub fn blocking_transfer_from_ram(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> { pub fn blocking_transfer_from_ram(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
self.blocking_inner(read, write) self.blocking_inner_from_ram(read, write)
} }
/// Simultaneously sends and receives data. /// Simultaneously sends and receives data.
@ -391,7 +391,7 @@ impl<'d, T: Instance> Spis<'d, T> {
/// Same as [`blocking_write`](Spis::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more. /// Same as [`blocking_write`](Spis::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
/// Returns number of bytes written. /// Returns number of bytes written.
pub fn blocking_write_from_ram(&mut self, data: &[u8]) -> Result<usize, Error> { pub fn blocking_write_from_ram(&mut self, data: &[u8]) -> Result<usize, Error> {
self.blocking_inner(&mut [], data).map(|n| n.1) self.blocking_inner_from_ram(&mut [], data).map(|n| n.1)
} }
/// Reads data from the SPI bus without sending anything. /// Reads data from the SPI bus without sending anything.