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Merge pull request #3423 from chrenderle/l5-flash
stm32/flash: add support for l5
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commit
a580437841
@ -23,6 +23,9 @@ pub(crate) unsafe fn lock() {
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w.set_prglock(true);
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w.set_pelock(true);
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});
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#[cfg(any(flash_l5))]
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pac::FLASH.nscr().modify(|w| w.set_nslock(true));
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}
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pub(crate) unsafe fn unlock() {
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@ -46,6 +49,14 @@ pub(crate) unsafe fn unlock() {
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pac::FLASH.prgkeyr().write_value(0x1314_1516);
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}
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}
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#[cfg(any(flash_l5))]
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{
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if pac::FLASH.nscr().read().nslock() {
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pac::FLASH.nskeyr().write_value(0x4567_0123);
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pac::FLASH.nskeyr().write_value(0xCDEF_89AB);
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}
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}
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}
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pub(crate) unsafe fn enable_blocking_write() {
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@ -53,11 +64,17 @@ pub(crate) unsafe fn enable_blocking_write() {
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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pac::FLASH.cr().write(|w| w.set_pg(true));
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#[cfg(any(flash_l5))]
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pac::FLASH.nscr().write(|w| w.set_nspg(true));
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}
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pub(crate) unsafe fn disable_blocking_write() {
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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pac::FLASH.cr().write(|w| w.set_pg(false));
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#[cfg(any(flash_l5))]
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pac::FLASH.nscr().write(|w| w.set_nspg(false));
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}
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pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
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@ -84,13 +101,25 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
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write_volatile(sector.start as *mut u32, 0xFFFFFFFF);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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#[cfg(any(flash_wl, flash_wb, flash_l4, flash_l5))]
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{
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let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
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#[cfg(flash_l4)]
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let (idx, bank) = if idx > 255 { (idx - 256, true) } else { (idx, false) };
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#[cfg(flash_l5)]
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let (idx, bank) = if pac::FLASH.optr().read().dbank() {
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if idx > 255 {
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(idx - 256, Some(true))
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} else {
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(idx, Some(false))
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}
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} else {
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(idx, None)
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};
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#[cfg(not(flash_l5))]
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pac::FLASH.cr().modify(|w| {
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w.set_per(true);
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w.set_pnb(idx as u8);
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@ -101,6 +130,16 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
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#[cfg(any(flash_l4))]
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w.set_bker(bank);
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});
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#[cfg(flash_l5)]
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pac::FLASH.nscr().modify(|w| {
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w.set_nsper(true);
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w.set_nspnb(idx as u8);
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if let Some(bank) = bank {
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w.set_nsbker(bank);
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}
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w.set_nsstrt(true);
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});
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}
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let ret: Result<(), Error> = wait_ready_blocking();
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@ -108,6 +147,9 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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pac::FLASH.cr().modify(|w| w.set_per(false));
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#[cfg(any(flash_l5))]
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pac::FLASH.nscr().modify(|w| w.set_nsper(false));
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#[cfg(any(flash_l0, flash_l1))]
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pac::FLASH.pecr().modify(|w| {
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w.set_erase(false);
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@ -121,11 +163,17 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
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pub(crate) unsafe fn clear_all_err() {
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// read and write back the same value.
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// This clears all "write 1 to clear" bits.
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#[cfg(not(flash_l5))]
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pac::FLASH.sr().modify(|_| {});
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#[cfg(flash_l5)]
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pac::FLASH.nssr().modify(|_| {});
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}
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unsafe fn wait_ready_blocking() -> Result<(), Error> {
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loop {
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#[cfg(not(flash_l5))]
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{
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let sr = pac::FLASH.sr().read();
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if !sr.bsy() {
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@ -159,4 +207,34 @@ unsafe fn wait_ready_blocking() -> Result<(), Error> {
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return Ok(());
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}
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}
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#[cfg(flash_l5)]
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{
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let nssr = pac::FLASH.nssr().read();
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if !nssr.nsbsy() {
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if nssr.nsprogerr() {
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return Err(Error::Prog);
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}
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if nssr.nswrperr() {
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return Err(Error::Protected);
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}
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if nssr.nspgaerr() {
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return Err(Error::Unaligned);
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}
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if nssr.nssizerr() {
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return Err(Error::Size);
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}
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if nssr.nspgserr() {
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return Err(Error::Seq);
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}
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return Ok(());
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}
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}
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}
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}
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@ -91,7 +91,7 @@ pub enum FlashBank {
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Bank2 = 1,
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}
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#[cfg_attr(any(flash_l0, flash_l1, flash_l4, flash_wl, flash_wb), path = "l.rs")]
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#[cfg_attr(any(flash_l0, flash_l1, flash_l4, flash_l5, flash_wl, flash_wb), path = "l.rs")]
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#[cfg_attr(flash_f0, path = "f0.rs")]
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#[cfg_attr(any(flash_f1, flash_f3), path = "f1f3.rs")]
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#[cfg_attr(flash_f2, path = "f2.rs")]
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@ -105,8 +105,9 @@ pub enum FlashBank {
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#[cfg_attr(flash_u0, path = "u0.rs")]
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#[cfg_attr(
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not(any(
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flash_l0, flash_l1, flash_l4, flash_wl, flash_wb, flash_f0, flash_f1, flash_f2, flash_f3, flash_f4, flash_f7,
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flash_g0, flash_g4c2, flash_g4c3, flash_g4c4, flash_h7, flash_h7ab, flash_u5, flash_h50, flash_u0
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flash_l0, flash_l1, flash_l4, flash_l5, flash_wl, flash_wb, flash_f0, flash_f1, flash_f2, flash_f3, flash_f4,
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flash_f7, flash_g0, flash_g0, flash_g4c2, flash_g4c3, flash_g4c4, flash_h7, flash_h7ab, flash_u5, flash_h50,
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flash_u0
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)),
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path = "other.rs"
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)]
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