From db56c4fe6fb919e89edda37fc5acb2fb05f45745 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=ABl=20Schulz-Ansres?= Date: Wed, 15 May 2024 12:54:30 +0200 Subject: [PATCH 1/8] Add miso pullup to spi configuration, add input as field for speed --- embassy-stm32/src/gpio.rs | 36 ++++++++++++++++++++++++++++++++++++ embassy-stm32/src/spi/mod.rs | 29 +++++++++++++++++++++++++++-- 2 files changed, 63 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs index 214813a42..d2db0a257 100644 --- a/embassy-stm32/src/gpio.rs +++ b/embassy-stm32/src/gpio.rs @@ -265,6 +265,7 @@ impl From for vals::Pupdr { #[derive(Debug, Copy, Clone)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Speed { + Input, Low, Medium, #[cfg(not(any(syscfg_f0, gpio_v1)))] @@ -278,6 +279,7 @@ impl From for vals::Mode { use Speed::*; match speed { + Input => vals::Mode::INPUT, Low => vals::Mode::OUTPUT2MHZ, Medium => vals::Mode::OUTPUT10MHZ, VeryHigh => vals::Mode::OUTPUT50MHZ, @@ -291,6 +293,7 @@ impl From for vals::Ospeedr { use Speed::*; match speed { + Input => vals::Ospeedr::LOWSPEED, Low => vals::Ospeedr::LOWSPEED, Medium => vals::Ospeedr::MEDIUMSPEED, #[cfg(not(syscfg_f0))] @@ -676,6 +679,39 @@ pub(crate) trait SealedPin { #[cfg(gpio_v2)] self.block().ospeedr().modify(|w| w.set_ospeedr(pin, speed.into())); } + + + /// Get the pull-up configuration. + #[inline] + fn pull(&self) -> Pull { + critical_section::with(|_| { + let r = self.block(); + let n = self._pin() as usize; + #[cfg(gpio_v1)] + { + let crlh = if n < 8 { 0 } else { 1 }; + match r.cr(crlh).cnf(n % 8) { + vals::CnfIn::FLOATING => Pull::None, + _ => if r.bsrr().read().bs(n % 8) { + Pull::Up + } else if r.bsrr().read().br(n % 8) { + Pull::Down + } else { + Pull::None + } + } + } + #[cfg(gpio_v2)] + { + match r.pupdr().read().pupdr(n % 8) { + vals::Pupdr::FLOATING => Pull::None, + vals::Pupdr::PULLDOWN => Pull::Down, + vals::Pupdr::PULLUP => Pull::Up, + vals::Pupdr::_RESERVED_3 => Pull::None, + } + } + }) + } } /// GPIO pin trait. diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs index c39ef1913..bcd6b0bf4 100644 --- a/embassy-stm32/src/spi/mod.rs +++ b/embassy-stm32/src/spi/mod.rs @@ -50,6 +50,11 @@ pub struct Config { pub bit_order: BitOrder, /// Clock frequency. pub frequency: Hertz, + /// Enable internal pullup on MISO. + /// + /// There are some ICs that require a pull-up on the MISO pin for some applications. + /// If you are unsure, you probably don't need this. + pub miso_pullup: bool, } impl Default for Config { @@ -58,6 +63,7 @@ impl Default for Config { mode: MODE_0, bit_order: BitOrder::MsbFirst, frequency: Hertz(1_000_000), + miso_pullup: false, } } } @@ -275,6 +281,16 @@ impl<'d, T: Instance, M: PeriMode> Spi<'d, T, M> { BitOrder::MsbFirst }; + let miso_pullup = match &self.miso { + None => false, + Some(pin) => + if pin.pull() == Pull::Up { + true + } else { + false + } + }; + #[cfg(any(spi_v1, spi_f1, spi_v2))] let br = cfg.br(); #[cfg(any(spi_v3, spi_v4, spi_v5))] @@ -287,6 +303,7 @@ impl<'d, T: Instance, M: PeriMode> Spi<'d, T, M> { mode: Mode { polarity, phase }, bit_order, frequency, + miso_pullup, } } @@ -409,7 +426,11 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> { peri, new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()), new_pin!(mosi, AFType::OutputPushPull, Speed::VeryHigh), - new_pin!(miso, AFType::Input, Speed::VeryHigh), + new_pin!(miso, AFType::Input, Speed::Input, + match config.miso_pullup { + true => Pull::Up, + false => Pull::None, + }), None, None, config, @@ -427,7 +448,11 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> { peri, new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()), None, - new_pin!(miso, AFType::Input, Speed::VeryHigh), + new_pin!(miso, AFType::Input, Speed::Input, + match config.miso_pullup { + true => Pull::Up, + false => Pull::None, + }), None, None, config, From cc6998be30856d05a4a6a975f35fd0e5df2ea807 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=ABl=20Schulz-Ansres?= Date: Wed, 15 May 2024 14:12:44 +0200 Subject: [PATCH 2/8] Cargo format --- embassy-stm32/src/gpio.rs | 15 ++++++++------- embassy-stm32/src/spi/mod.rs | 27 ++++++++++++++++++--------- 2 files changed, 26 insertions(+), 16 deletions(-) diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs index d2db0a257..7de223455 100644 --- a/embassy-stm32/src/gpio.rs +++ b/embassy-stm32/src/gpio.rs @@ -680,7 +680,6 @@ pub(crate) trait SealedPin { self.block().ospeedr().modify(|w| w.set_ospeedr(pin, speed.into())); } - /// Get the pull-up configuration. #[inline] fn pull(&self) -> Pull { @@ -692,12 +691,14 @@ pub(crate) trait SealedPin { let crlh = if n < 8 { 0 } else { 1 }; match r.cr(crlh).cnf(n % 8) { vals::CnfIn::FLOATING => Pull::None, - _ => if r.bsrr().read().bs(n % 8) { - Pull::Up - } else if r.bsrr().read().br(n % 8) { - Pull::Down - } else { - Pull::None + _ => { + if r.bsrr().read().bs(n % 8) { + Pull::Up + } else if r.bsrr().read().br(n % 8) { + Pull::Down + } else { + Pull::None + } } } } diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs index bcd6b0bf4..76d58def6 100644 --- a/embassy-stm32/src/spi/mod.rs +++ b/embassy-stm32/src/spi/mod.rs @@ -283,11 +283,12 @@ impl<'d, T: Instance, M: PeriMode> Spi<'d, T, M> { let miso_pullup = match &self.miso { None => false, - Some(pin) => - if pin.pull() == Pull::Up { - true - } else { - false + Some(pin) => { + if pin.pull() == Pull::Up { + true + } else { + false + } } }; @@ -426,11 +427,15 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> { peri, new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()), new_pin!(mosi, AFType::OutputPushPull, Speed::VeryHigh), - new_pin!(miso, AFType::Input, Speed::Input, + new_pin!( + miso, + AFType::Input, + Speed::Input, match config.miso_pullup { true => Pull::Up, false => Pull::None, - }), + } + ), None, None, config, @@ -448,11 +453,15 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> { peri, new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()), None, - new_pin!(miso, AFType::Input, Speed::Input, + new_pin!( + miso, + AFType::Input, + Speed::Input, match config.miso_pullup { true => Pull::Up, false => Pull::None, - }), + } + ), None, None, config, From 2f7bba4668006ed3124adf6c94efeb2169d79a9c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=ABl=20Schulz-Ansres?= Date: Wed, 22 May 2024 23:44:34 +0200 Subject: [PATCH 3/8] Use ODR register for Pull::Up or Down --- embassy-stm32/src/gpio.rs | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs index 7de223455..3fb7fda57 100644 --- a/embassy-stm32/src/gpio.rs +++ b/embassy-stm32/src/gpio.rs @@ -689,17 +689,19 @@ pub(crate) trait SealedPin { #[cfg(gpio_v1)] { let crlh = if n < 8 { 0 } else { 1 }; - match r.cr(crlh).cnf(n % 8) { - vals::CnfIn::FLOATING => Pull::None, - _ => { - if r.bsrr().read().bs(n % 8) { - Pull::Up - } else if r.bsrr().read().br(n % 8) { - Pull::Down - } else { - Pull::None + match r.cr(crlh).read().mode(n % 8) { + vals::Mode::INPUT => { + match r.cr(crlh).read().cnf_in(n % 8) { + vals::CnfIn::PULL => { + match r.odr().read().odr(n % 8) { + vals::Odr::LOW => Pull::Down, + vals::Odr::HIGH => Pull::Up + } + }, + _ => Pull::None } - } + }, + _ => Pull::None } } #[cfg(gpio_v2)] From 89017d338f407e8e5319cccf97b2d47900f58b81 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=ABl=20Schulz-Ansres?= Date: Wed, 22 May 2024 23:45:26 +0200 Subject: [PATCH 4/8] Cargo format --- embassy-stm32/src/gpio.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs index 3fb7fda57..fb3b79a36 100644 --- a/embassy-stm32/src/gpio.rs +++ b/embassy-stm32/src/gpio.rs @@ -690,18 +690,14 @@ pub(crate) trait SealedPin { { let crlh = if n < 8 { 0 } else { 1 }; match r.cr(crlh).read().mode(n % 8) { - vals::Mode::INPUT => { - match r.cr(crlh).read().cnf_in(n % 8) { - vals::CnfIn::PULL => { - match r.odr().read().odr(n % 8) { - vals::Odr::LOW => Pull::Down, - vals::Odr::HIGH => Pull::Up - } - }, - _ => Pull::None - } + vals::Mode::INPUT => match r.cr(crlh).read().cnf_in(n % 8) { + vals::CnfIn::PULL => match r.odr().read().odr(n % 8) { + vals::Odr::LOW => Pull::Down, + vals::Odr::HIGH => Pull::Up, + }, + _ => Pull::None, }, - _ => Pull::None + _ => Pull::None, } } #[cfg(gpio_v2)] From 27e8ef6e7e720a3c74f7c696ab105915695431c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=ABl=20Schulz-Ansres?= Date: Wed, 22 May 2024 23:49:48 +0200 Subject: [PATCH 5/8] Remove Speed::Input in order to move it into separate PR --- embassy-stm32/src/gpio.rs | 3 --- embassy-stm32/src/spi/mod.rs | 4 ++-- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs index fb3b79a36..9f28c8ec2 100644 --- a/embassy-stm32/src/gpio.rs +++ b/embassy-stm32/src/gpio.rs @@ -265,7 +265,6 @@ impl From for vals::Pupdr { #[derive(Debug, Copy, Clone)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Speed { - Input, Low, Medium, #[cfg(not(any(syscfg_f0, gpio_v1)))] @@ -279,7 +278,6 @@ impl From for vals::Mode { use Speed::*; match speed { - Input => vals::Mode::INPUT, Low => vals::Mode::OUTPUT2MHZ, Medium => vals::Mode::OUTPUT10MHZ, VeryHigh => vals::Mode::OUTPUT50MHZ, @@ -293,7 +291,6 @@ impl From for vals::Ospeedr { use Speed::*; match speed { - Input => vals::Ospeedr::LOWSPEED, Low => vals::Ospeedr::LOWSPEED, Medium => vals::Ospeedr::MEDIUMSPEED, #[cfg(not(syscfg_f0))] diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs index 76d58def6..24159adce 100644 --- a/embassy-stm32/src/spi/mod.rs +++ b/embassy-stm32/src/spi/mod.rs @@ -430,7 +430,7 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> { new_pin!( miso, AFType::Input, - Speed::Input, + Speed::VeryHigh, match config.miso_pullup { true => Pull::Up, false => Pull::None, @@ -456,7 +456,7 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> { new_pin!( miso, AFType::Input, - Speed::Input, + Speed::VeryHigh, match config.miso_pullup { true => Pull::Up, false => Pull::None, From f285a545be80772d1b9dd0d98f8ec89184deb388 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=ABl=20Schulz-Ansres?= Date: Thu, 23 May 2024 23:52:18 +0200 Subject: [PATCH 6/8] Change bool to Pull --- embassy-stm32/src/spi/mod.rs | 34 ++++++---------------------------- 1 file changed, 6 insertions(+), 28 deletions(-) diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs index be8cfcecf..9238e0f6f 100644 --- a/embassy-stm32/src/spi/mod.rs +++ b/embassy-stm32/src/spi/mod.rs @@ -54,7 +54,7 @@ pub struct Config { /// /// There are some ICs that require a pull-up on the MISO pin for some applications. /// If you are unsure, you probably don't need this. - pub miso_pullup: bool, + pub miso_pullup: Pull, } impl Default for Config { @@ -63,7 +63,7 @@ impl Default for Config { mode: MODE_0, bit_order: BitOrder::MsbFirst, frequency: Hertz(1_000_000), - miso_pullup: false, + miso_pullup: Pull::None, } } } @@ -280,14 +280,8 @@ impl<'d, M: PeriMode> Spi<'d, M> { }; let miso_pullup = match &self.miso { - None => false, - Some(pin) => { - if pin.pull() == Pull::Up { - true - } else { - false - } - } + None => Pull::None, + Some(pin) => pin.pull(), }; #[cfg(any(spi_v1, spi_f1, spi_v2))] @@ -424,15 +418,7 @@ impl<'d> Spi<'d, Blocking> { peri, new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()), new_pin!(mosi, AFType::OutputPushPull, Speed::VeryHigh), - new_pin!( - miso, - AFType::Input, - Speed::VeryHigh, - match config.miso_pullup { - true => Pull::Up, - false => Pull::None, - } - ), + new_pin!(miso, AFType::Input, Speed::VeryHigh, config.miso_pullup), None, None, config, @@ -450,15 +436,7 @@ impl<'d> Spi<'d, Blocking> { peri, new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()), None, - new_pin!( - miso, - AFType::Input, - Speed::VeryHigh, - match config.miso_pullup { - true => Pull::Up, - false => Pull::None, - } - ), + new_pin!(miso, AFType::Input, Speed::VeryHigh, config.miso_pullup), None, None, config, From 5cba97821f6f3e716452d38bb0c645b51592abc0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=ABl=20Schulz-Ansres?= Date: Fri, 24 May 2024 01:05:56 +0200 Subject: [PATCH 7/8] Naming: Change pullup to pull --- embassy-stm32/src/spi/mod.rs | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs index 9238e0f6f..5fc8691ac 100644 --- a/embassy-stm32/src/spi/mod.rs +++ b/embassy-stm32/src/spi/mod.rs @@ -54,7 +54,7 @@ pub struct Config { /// /// There are some ICs that require a pull-up on the MISO pin for some applications. /// If you are unsure, you probably don't need this. - pub miso_pullup: Pull, + pub miso_pull: Pull, } impl Default for Config { @@ -63,7 +63,7 @@ impl Default for Config { mode: MODE_0, bit_order: BitOrder::MsbFirst, frequency: Hertz(1_000_000), - miso_pullup: Pull::None, + miso_pull: Pull::None, } } } @@ -279,7 +279,7 @@ impl<'d, M: PeriMode> Spi<'d, M> { BitOrder::MsbFirst }; - let miso_pullup = match &self.miso { + let miso_pull = match &self.miso { None => Pull::None, Some(pin) => pin.pull(), }; @@ -295,7 +295,7 @@ impl<'d, M: PeriMode> Spi<'d, M> { mode: Mode { polarity, phase }, bit_order, frequency, - miso_pullup, + miso_pull, } } @@ -418,7 +418,7 @@ impl<'d> Spi<'d, Blocking> { peri, new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()), new_pin!(mosi, AFType::OutputPushPull, Speed::VeryHigh), - new_pin!(miso, AFType::Input, Speed::VeryHigh, config.miso_pullup), + new_pin!(miso, AFType::Input, Speed::VeryHigh, config.miso_pull), None, None, config, @@ -436,7 +436,7 @@ impl<'d> Spi<'d, Blocking> { peri, new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()), None, - new_pin!(miso, AFType::Input, Speed::VeryHigh, config.miso_pullup), + new_pin!(miso, AFType::Input, Speed::VeryHigh, config.miso_pull), None, None, config, From ac76a713e1dbf4b3b3de9b3017256a708b335452 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=ABl=20Schulz-Andres?= Date: Fri, 24 May 2024 16:54:04 +0200 Subject: [PATCH 8/8] Remove wrong modulo --- embassy-stm32/src/gpio.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs index 9f28c8ec2..6a00b70ec 100644 --- a/embassy-stm32/src/gpio.rs +++ b/embassy-stm32/src/gpio.rs @@ -688,7 +688,7 @@ pub(crate) trait SealedPin { let crlh = if n < 8 { 0 } else { 1 }; match r.cr(crlh).read().mode(n % 8) { vals::Mode::INPUT => match r.cr(crlh).read().cnf_in(n % 8) { - vals::CnfIn::PULL => match r.odr().read().odr(n % 8) { + vals::CnfIn::PULL => match r.odr().read().odr(n) { vals::Odr::LOW => Pull::Down, vals::Odr::HIGH => Pull::Up, }, @@ -699,7 +699,7 @@ pub(crate) trait SealedPin { } #[cfg(gpio_v2)] { - match r.pupdr().read().pupdr(n % 8) { + match r.pupdr().read().pupdr(n) { vals::Pupdr::FLOATING => Pull::None, vals::Pupdr::PULLDOWN => Pull::Down, vals::Pupdr::PULLUP => Pull::Up,