mirror of
https://github.com/embassy-rs/embassy.git
synced 2024-11-22 14:53:03 +00:00
fix interrupts
This commit is contained in:
parent
2ee2d18465
commit
9bf09488f1
@ -5,6 +5,8 @@
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//! are dropped correctly (e.g. not using `mem::forget()`).
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//! are dropped correctly (e.g. not using `mem::forget()`).
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use core::future::Future;
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use core::future::Future;
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use core::ptr;
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use core::sync::atomic::{self, Ordering};
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use core::task::{Context, Poll};
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use core::task::{Context, Poll};
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use embassy::interrupt::OwnedInterrupt;
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use embassy::interrupt::OwnedInterrupt;
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@ -33,31 +35,32 @@ use crate::pac::{DMA2, USART1};
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/// Interface to the Serial peripheral
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/// Interface to the Serial peripheral
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pub struct Serial<USART: PeriAddress<MemSize = u8>, TSTREAM: Stream, RSTREAM: Stream> {
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pub struct Serial<USART: PeriAddress<MemSize = u8>, TSTREAM: Stream, RSTREAM: Stream> {
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// tx_transfer: Transfer<Stream7<DMA2>, Channel4, USART1, MemoryToPeripheral, &mut [u8; 20]>,
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// rx_transfer: Transfer<Stream2<DMA2>, Channel4, USART1, PeripheralToMemory, &mut [u8; 20]>,
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tx_stream: Option<TSTREAM>,
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tx_stream: Option<TSTREAM>,
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rx_stream: Option<RSTREAM>,
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rx_stream: Option<RSTREAM>,
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usart: Option<USART>,
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usart: Option<USART>,
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tx_int: interrupt::DMA2_STREAM7Interrupt,
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rx_int: interrupt::DMA2_STREAM2Interrupt,
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usart_int: interrupt::USART1Interrupt,
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}
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}
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struct State {
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struct State {
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tx_done: Signal<()>,
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tx_int: Signal<()>,
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rx_done: Signal<()>,
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rx_int: Signal<()>,
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dma_done: Signal<()>,
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}
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}
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static STATE: State = State {
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static STATE: State = State {
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tx_done: Signal::new(),
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tx_int: Signal::new(),
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rx_done: Signal::new(),
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rx_int: Signal::new(),
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dma_done: Signal::new(),
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};
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};
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static mut INSTANCE: *const Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> = ptr::null_mut();
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impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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pub fn new(
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pub fn new(
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txd: PA9<Alternate<AF7>>,
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txd: PA9<Alternate<AF7>>,
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rxd: PA10<Alternate<AF7>>,
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rxd: PA10<Alternate<AF7>>,
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tx_int: interrupt::DMA2_STREAM2Interrupt,
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tx_int: interrupt::DMA2_STREAM7Interrupt,
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rx_int: interrupt::DMA2_STREAM7Interrupt,
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rx_int: interrupt::DMA2_STREAM2Interrupt,
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usart_int: interrupt::USART1Interrupt,
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usart_int: interrupt::USART1Interrupt,
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dma: DMA2,
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dma: DMA2,
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usart: USART1,
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usart: USART1,
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@ -80,20 +83,14 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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.unwrap();
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.unwrap();
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serial.listen(SerialEvent::Idle);
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serial.listen(SerialEvent::Idle);
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serial.listen(SerialEvent::Txe);
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// serial.listen(SerialEvent::Txe);
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let (usart, _) = serial.release();
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let (usart, _) = serial.release();
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// Register ISR
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// Register ISR
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tx_int.set_handler(Self::on_tx_irq);
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tx_int.set_handler(Self::on_tx_irq);
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tx_int.unpend();
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tx_int.enable();
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rx_int.set_handler(Self::on_rx_irq);
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rx_int.set_handler(Self::on_rx_irq);
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rx_int.unpend();
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usart_int.set_handler(Self::on_rx_irq);
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rx_int.enable();
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// usart_int.set_handler(Self::on_usart_irq);
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// usart_int.unpend();
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// usart_int.unpend();
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// usart_int.enable();
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// usart_int.enable();
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@ -103,40 +100,56 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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tx_stream: Some(streams.7),
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tx_stream: Some(streams.7),
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rx_stream: Some(streams.2),
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rx_stream: Some(streams.2),
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usart: Some(usart),
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usart: Some(usart),
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tx_int: tx_int,
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rx_int: rx_int,
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usart_int: usart_int,
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}
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}
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}
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}
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unsafe fn on_tx_irq() {
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unsafe fn on_tx_irq() {
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STATE.tx_done.signal(());
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let s = &(*INSTANCE);
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s.tx_int.disable();
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STATE.tx_int.signal(());
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}
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}
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unsafe fn on_rx_irq() {
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unsafe fn on_rx_irq() {
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STATE.rx_done.signal(());
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let s = &(*INSTANCE);
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atomic::compiler_fence(Ordering::Acquire);
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s.rx_int.disable();
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s.usart_int.disable();
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atomic::compiler_fence(Ordering::Release);
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STATE.rx_int.signal(());
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}
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}
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unsafe fn on_usart_irq() {
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unsafe fn on_usart_irq() {
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/*
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let s = &(*INSTANCE);
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TODO: Signal tx_done if txe
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*/
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/*
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atomic::compiler_fence(Ordering::Acquire);
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TODO: Signal rx_done if idle
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s.rx_int.disable();
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*/
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s.usart_int.disable();
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atomic::compiler_fence(Ordering::Release);
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// STATE.rx_done.signal(());
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STATE.rx_int.signal(());
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}
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}
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/// Sends serial data.
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/// Sends serial data.
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///
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///
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/// `tx_buffer` is marked as static as per `embedded-dma` requirements.
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/// `tx_buffer` is marked as static as per `embedded-dma` requirements.
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/// It it safe to use a buffer with a non static lifetime if memory is not
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/// It it safe to use a buffer with a non static lifetime if memory is not
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/// reused until the future has finished.
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/// reused until the future has finished.
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pub fn send<'a, B>(&'a mut self, tx_buffer: B) -> impl Future<Output = ()> + 'a
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pub fn send<'a, B: 'a>(&'a mut self, tx_buffer: B) -> impl Future<Output = ()> + 'a
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where
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where
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B: WriteBuffer<Word = u8> + 'static,
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B: StaticWriteBuffer<Word = u8>,
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{
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{
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unsafe { INSTANCE = self };
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let tx_stream = self.tx_stream.take().unwrap();
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let tx_stream = self.tx_stream.take().unwrap();
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let usart = self.usart.take().unwrap();
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let usart = self.usart.take().unwrap();
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STATE.tx_done.reset();
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STATE.tx_int.reset();
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async move {
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async move {
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let mut tx_transfer = Transfer::init(
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let mut tx_transfer = Transfer::init(
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@ -150,9 +163,11 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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.double_buffer(false),
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.double_buffer(false),
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);
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);
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self.tx_int.unpend();
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self.tx_int.enable();
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tx_transfer.start(|_usart| {});
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tx_transfer.start(|_usart| {});
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STATE.tx_done.wait().await;
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STATE.tx_int.wait().await;
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let (tx_stream, usart, _buf, _) = tx_transfer.free();
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let (tx_stream, usart, _buf, _) = tx_transfer.free();
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self.tx_stream.replace(tx_stream);
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self.tx_stream.replace(tx_stream);
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@ -170,13 +185,15 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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/// `rx_buffer` is marked as static as per `embedded-dma` requirements.
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/// `rx_buffer` is marked as static as per `embedded-dma` requirements.
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/// It it safe to use a buffer with a non static lifetime if memory is not
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/// It it safe to use a buffer with a non static lifetime if memory is not
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/// reused until the future has finished.
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/// reused until the future has finished.
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pub fn receive<'a, B>(&'a mut self, rx_buffer: B) -> impl Future<Output = B> + 'a
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pub fn receive<'a, B: 'a>(&'a mut self, rx_buffer: B) -> impl Future<Output = B> + 'a
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where
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where
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B: WriteBuffer<Word = u8> + 'static + Unpin,
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B: StaticWriteBuffer<Word = u8> + Unpin,
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{
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{
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unsafe { INSTANCE = self };
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let rx_stream = self.rx_stream.take().unwrap();
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let rx_stream = self.rx_stream.take().unwrap();
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let usart = self.usart.take().unwrap();
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let usart = self.usart.take().unwrap();
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STATE.rx_done.reset();
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STATE.rx_int.reset();
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async move {
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async move {
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let mut rx_transfer = Transfer::init(
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let mut rx_transfer = Transfer::init(
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@ -190,9 +207,12 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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.double_buffer(false),
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.double_buffer(false),
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);
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);
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self.rx_int.unpend();
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self.rx_int.enable();
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rx_transfer.start(|_usart| {});
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rx_transfer.start(|_usart| {});
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STATE.rx_done.wait().await;
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STATE.rx_int.wait().await;
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let (rx_stream, usart, buf, _) = rx_transfer.free();
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let (rx_stream, usart, buf, _) = rx_transfer.free();
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self.rx_stream.replace(rx_stream);
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self.rx_stream.replace(rx_stream);
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