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Merge pull request #3337 from doesnotcompete/feature/h7rs-usb

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Add OTG_HS support for STM32H7R/S
This commit is contained in:
Dario Nieuwenhuis 2024-09-22 23:56:17 +00:00 committed by GitHub
commit 9705f3332b
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GPG Key ID: B5690EEEBB952194
8 changed files with 456 additions and 7 deletions
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4
embassy-stm32/Cargo.toml
View File

@ -72,7 +72,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ad00827345b4b758b2453082809d6e3b634b5364" }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-acaf04256034066bd5b3a8426224ccf3e4cb7d19" }
vcell = "0.1.3"
nb = "1.0.0"
@ -99,7 +99,7 @@ proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ad00827345b4b758b2453082809d6e3b634b5364", default-features = false, features = ["metadata"] }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-acaf04256034066bd5b3a8426224ccf3e4cb7d19", default-features = false, features = ["metadata"] }
[features]
default = ["rt"]

4
embassy-stm32/build.rs
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@ -55,7 +55,7 @@ fn main() {
let mut singletons: Vec<String> = Vec::new();
for p in METADATA.peripherals {
if let Some(r) = &p.registers {
if r.kind == "adccommon" || r.kind == "sai" || r.kind == "ucpd" {
if r.kind == "adccommon" || r.kind == "sai" || r.kind == "ucpd" || r.kind == "otg" {
// TODO: should we emit this for all peripherals? if so, we will need a list of all
// possible peripherals across all chips, so that we can declare the configs
// (replacing the hard-coded list of `peri_*` cfgs below)
@ -111,6 +111,8 @@ fn main() {
"peri_sai4",
"peri_ucpd1",
"peri_ucpd2",
"peri_usb_otg_fs",
"peri_usb_otg_hs",
]);
cfgs.declare_all(&["mco", "mco1", "mco2"]);

36
embassy-stm32/src/rcc/h.rs
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@ -34,8 +34,10 @@ pub enum VoltageScale {
Scale2,
Scale3,
}
#[cfg(any(stm32h7rs))]
#[cfg(stm32h7rs)]
pub use crate::pac::pwr::vals::Vos as VoltageScale;
#[cfg(all(stm32h7rs, peri_usb_otg_hs))]
pub use crate::pac::rcc::vals::{Usbphycsel, Usbrefcksel};
#[derive(Clone, Copy, Eq, PartialEq)]
pub enum HseMode {
@ -557,6 +559,27 @@ pub(crate) unsafe fn init(config: Config) {
let rtc = config.ls.init();
#[cfg(all(stm32h7rs, peri_usb_otg_hs))]
let usb_refck = match config.mux.usbphycsel {
Usbphycsel::HSE => hse,
Usbphycsel::HSE_DIV_2 => hse.map(|hse_val| hse_val / 2u8),
Usbphycsel::PLL3_Q => pll3.q,
_ => None,
};
#[cfg(all(stm32h7rs, peri_usb_otg_hs))]
let usb_refck_sel = match usb_refck {
Some(clk_val) => match clk_val {
Hertz(16_000_000) => Usbrefcksel::MHZ16,
Hertz(19_200_000) => Usbrefcksel::MHZ19_2,
Hertz(20_000_000) => Usbrefcksel::MHZ20,
Hertz(24_000_000) => Usbrefcksel::MHZ24,
Hertz(26_000_000) => Usbrefcksel::MHZ26,
Hertz(32_000_000) => Usbrefcksel::MHZ32,
_ => panic!("cannot select USBPHYC reference clock with source frequency of {} Hz, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
},
None => Usbrefcksel::MHZ24,
};
#[cfg(stm32h7)]
{
RCC.d1cfgr().modify(|w| {
@ -593,6 +616,11 @@ pub(crate) unsafe fn init(config: Config) {
w.set_ppre4(config.apb4_pre);
w.set_ppre5(config.apb5_pre);
});
#[cfg(peri_usb_otg_hs)]
RCC.ahbperckselr().modify(|w| {
w.set_usbrefcksel(usb_refck_sel);
});
}
#[cfg(stm32h5)]
{
@ -698,7 +726,9 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(stm32h7rs)]
clk48mohci: None, // TODO
#[cfg(stm32h7rs)]
usb: None, // TODO
hse_div_2: hse.map(|clk| clk / 2u32),
#[cfg(stm32h7rs)]
usb: Some(Hertz(48_000_000)),
);
}
@ -769,7 +799,7 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
if num == 0 {
// on PLL1, DIVP must be even for most series.
// The enum value is 1 less than the divider, so check it's odd.
#[cfg(not(pwr_h7rm0468))]
#[cfg(not(any(pwr_h7rm0468, stm32h7rs)))]
assert!(div.to_bits() % 2 == 1);
#[cfg(pwr_h7rm0468)]
assert!(div.to_bits() % 2 == 1 || div.to_bits() == 0);

30
embassy-stm32/src/usb/mod.rs
View File

@ -13,9 +13,19 @@ fn common_init<T: Instance>() {
// Check the USB clock is enabled and running at exactly 48 MHz.
// frequency() will panic if not enabled
let freq = T::frequency();
// On the H7RS, the USBPHYC embeds a PLL accepting one of the input frequencies listed below and providing 48MHz to OTG_FS and 60MHz to OTG_HS internally
#[cfg(stm32h7rs)]
if ![16_000_000, 19_200_000, 20_000_000, 24_000_000, 26_000_000, 32_000_000].contains(&freq.0) {
panic!(
"USB clock should be one of 16, 19.2, 20, 24, 26, 32Mhz but is {} Hz. Please double-check your RCC settings.",
freq.0
)
}
// Check frequency is within the 0.25% tolerance allowed by the spec.
// Clock might not be exact 48Mhz due to rounding errors in PLL calculation, or if the user
// has tight clock restrictions due to something else (like audio).
#[cfg(not(stm32h7rs))]
if freq.0.abs_diff(48_000_000) > 120_000 {
panic!(
"USB clock should be 48Mhz but is {} Hz. Please double-check your RCC settings.",
@ -48,6 +58,26 @@ fn common_init<T: Instance>() {
while !crate::pac::PWR.cr3().read().usb33rdy() {}
}
#[cfg(stm32h7rs)]
{
// If true, VDD33USB is generated by internal regulator from VDD50USB
// If false, VDD33USB and VDD50USB must be suplied directly with 3.3V (default on nucleo)
// TODO: unhardcode
let internal_regulator = false;
// Enable USB power
critical_section::with(|_| {
crate::pac::PWR.csr2().modify(|w| {
w.set_usbregen(internal_regulator);
w.set_usb33den(true);
w.set_usbhsregen(true);
})
});
// Wait for USB power to stabilize
while !crate::pac::PWR.csr2().read().usb33rdy() {}
}
#[cfg(stm32u5)]
{
// Enable USB power

55
embassy-stm32/src/usb/otg.rs
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@ -97,6 +97,45 @@ impl<'d, T: Instance> Driver<'d, T> {
}
}
/// Initializes USB OTG peripheral with internal High-Speed PHY.
///
/// # Arguments
///
/// * `ep_out_buffer` - An internal buffer used to temporarily store received packets.
/// Must be large enough to fit all OUT endpoint max packet sizes.
/// Endpoint allocation will fail if it is too small.
pub fn new_hs(
_peri: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
dp: impl Peripheral<P = impl DpPin<T>> + 'd,
dm: impl Peripheral<P = impl DmPin<T>> + 'd,
ep_out_buffer: &'d mut [u8],
config: Config,
) -> Self {
into_ref!(dp, dm);
dp.set_as_af(dp.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
dm.set_as_af(dm.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
let regs = T::regs();
let instance = OtgInstance {
regs,
state: T::state(),
fifo_depth_words: T::FIFO_DEPTH_WORDS,
extra_rx_fifo_words: RX_FIFO_EXTRA_SIZE_WORDS,
endpoint_count: T::ENDPOINT_COUNT,
phy_type: PhyType::InternalHighSpeed,
quirk_setup_late_cnak: quirk_setup_late_cnak(regs),
calculate_trdt_fn: calculate_trdt::<T>,
};
Self {
inner: OtgDriver::new(ep_out_buffer, instance, config),
phantom: PhantomData,
}
}
/// Initializes USB OTG peripheral with external Full-speed PHY (usually, a High-speed PHY in Full-speed mode).
///
/// # Arguments
@ -272,6 +311,19 @@ impl<'d, T: Instance> Bus<'d, T> {
}
});
#[cfg(stm32h7rs)]
critical_section::with(|_| {
let rcc = crate::pac::RCC;
rcc.ahb1enr().modify(|w| {
w.set_usbphycen(true);
w.set_usb_otg_hsen(true);
});
rcc.ahb1lpenr().modify(|w| {
w.set_usbphyclpen(true);
w.set_usb_otg_hslpen(true);
});
});
let r = T::regs();
let core_id = r.cid().read().0;
trace!("Core id {:08x}", core_id);
@ -286,6 +338,7 @@ impl<'d, T: Instance> Bus<'d, T> {
match core_id {
0x0000_1200 | 0x0000_1100 => self.inner.config_v1(),
0x0000_2000 | 0x0000_2100 | 0x0000_2300 | 0x0000_3000 | 0x0000_3100 => self.inner.config_v2v3(),
0x0000_5000 => self.inner.config_v5(),
_ => unimplemented!("Unknown USB core id {:X}", core_id),
}
}
@ -501,7 +554,7 @@ fn calculate_trdt<T: Instance>(speed: Dspd) -> u8 {
match speed {
Dspd::HIGH_SPEED => {
// From RM0431 (F72xx), RM0090 (F429), RM0390 (F446)
if ahb_freq >= 30_000_000 {
if ahb_freq >= 30_000_000 || cfg!(stm32h7rs) {
0x9
} else {
panic!("AHB frequency is too low")

23
embassy-usb-synopsys-otg/src/lib.rs
View File

@ -584,6 +584,29 @@ impl<'d, const MAX_EP_COUNT: usize> Bus<'d, MAX_EP_COUNT> {
});
}
/// Applies configuration specific to
/// Core ID 0x0000_5000
pub fn config_v5(&mut self) {
let r = self.instance.regs;
let phy_type = self.instance.phy_type;
if phy_type == PhyType::InternalHighSpeed {
r.gccfg_v3().modify(|w| {
w.set_vbvaloven(!self.config.vbus_detection);
w.set_vbvaloval(!self.config.vbus_detection);
w.set_vbden(self.config.vbus_detection);
});
} else {
r.gotgctl().modify(|w| {
w.set_bvaloen(!self.config.vbus_detection);
w.set_bvaloval(!self.config.vbus_detection);
});
r.gccfg_v3().modify(|w| {
w.set_vbden(self.config.vbus_detection);
});
}
}
fn init(&mut self) {
let r = self.instance.regs;
let phy_type = self.instance.phy_type;

171
embassy-usb-synopsys-otg/src/otg_v1.rs
View File

@ -186,6 +186,11 @@ impl Otg {
pub const fn gccfg_v2(self) -> Reg<regs::GccfgV2, RW> {
unsafe { Reg::from_ptr(self.ptr.add(0x38usize) as _) }
}
#[doc = "General core configuration register, for core_id 0x0000_5xxx"]
#[inline(always)]
pub const fn gccfg_v3(self) -> Reg<regs::GccfgV3, RW> {
unsafe { Reg::from_ptr(self.ptr.add(0x38usize) as _) }
}
#[doc = "Core ID register"]
#[inline(always)]
pub const fn cid(self) -> Reg<regs::Cid, RW> {
@ -1831,6 +1836,172 @@ pub mod regs {
GccfgV2(0)
}
}
#[doc = "OTG general core configuration register."]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct GccfgV3(pub u32);
impl GccfgV3 {
#[doc = "Charger detection, result of the current mode (primary or secondary)."]
#[inline(always)]
pub const fn chgdet(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Charger detection, result of the current mode (primary or secondary)."]
#[inline(always)]
pub fn set_chgdet(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Single-Ended DP indicator This bit gives the voltage level on DP (also result of the comparison with V<sub>LGC</sub> threshold as defined in BC v1.2 standard)."]
#[inline(always)]
pub const fn fsvplus(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Single-Ended DP indicator This bit gives the voltage level on DP (also result of the comparison with V<sub>LGC</sub> threshold as defined in BC v1.2 standard)."]
#[inline(always)]
pub fn set_fsvplus(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Single-Ended DM indicator This bit gives the voltage level on DM (also result of the comparison with V<sub>LGC</sub> threshold as defined in BC v1.2 standard)."]
#[inline(always)]
pub const fn fsvminus(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Single-Ended DM indicator This bit gives the voltage level on DM (also result of the comparison with V<sub>LGC</sub> threshold as defined in BC v1.2 standard)."]
#[inline(always)]
pub fn set_fsvminus(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "VBUS session indicator Indicates if VBUS is above VBUS session threshold."]
#[inline(always)]
pub const fn sessvld(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "VBUS session indicator Indicates if VBUS is above VBUS session threshold."]
#[inline(always)]
pub fn set_sessvld(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "Host CDP behavior enable."]
#[inline(always)]
pub const fn hcdpen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Host CDP behavior enable."]
#[inline(always)]
pub fn set_hcdpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Host CDP port voltage detector enable on DP."]
#[inline(always)]
pub const fn hcdpdeten(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "Host CDP port voltage detector enable on DP."]
#[inline(always)]
pub fn set_hcdpdeten(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "Host CDP port Voltage source enable on DM."]
#[inline(always)]
pub const fn hvdmsrcen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "Host CDP port Voltage source enable on DM."]
#[inline(always)]
pub fn set_hvdmsrcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "Data Contact Detection enable."]
#[inline(always)]
pub const fn dcden(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "Data Contact Detection enable."]
#[inline(always)]
pub fn set_dcden(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "Primary detection enable."]
#[inline(always)]
pub const fn pden(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "Primary detection enable."]
#[inline(always)]
pub fn set_pden(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "VBUS detection enable Enables VBUS Sensing Comparators in order to detect VBUS presence and/or perform OTG operation."]
#[inline(always)]
pub const fn vbden(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "VBUS detection enable Enables VBUS Sensing Comparators in order to detect VBUS presence and/or perform OTG operation."]
#[inline(always)]
pub fn set_vbden(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "Secondary detection enable."]
#[inline(always)]
pub const fn sden(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "Secondary detection enable."]
#[inline(always)]
pub fn set_sden(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "Software override value of the VBUS B-session detection."]
#[inline(always)]
pub const fn vbvaloval(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "Software override value of the VBUS B-session detection."]
#[inline(always)]
pub fn set_vbvaloval(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "Enables a software override of the VBUS B-session detection."]
#[inline(always)]
pub const fn vbvaloven(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Enables a software override of the VBUS B-session detection."]
#[inline(always)]
pub fn set_vbvaloven(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Force host mode pull-downs If the ID pin functions are enabled, the host mode pull-downs on DP and DM activate automatically. However, whenever that is not the case, yet host mode is required, this bit must be used to force the pull-downs active."]
#[inline(always)]
pub const fn forcehostpd(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "Force host mode pull-downs If the ID pin functions are enabled, the host mode pull-downs on DP and DM activate automatically. However, whenever that is not the case, yet host mode is required, this bit must be used to force the pull-downs active."]
#[inline(always)]
pub fn set_forcehostpd(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
}
impl Default for GccfgV3 {
#[inline(always)]
fn default() -> GccfgV3 {
GccfgV3(0)
}
}
#[doc = "I2C access register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]

140
examples/stm32h7rs/src/bin/usb_serial.rs Normal file
View File

@ -0,0 +1,140 @@
#![no_std]
#![no_main]
use defmt::{panic, *};
use embassy_executor::Spawner;
use embassy_futures::join::join;
use embassy_stm32::time::Hertz;
use embassy_stm32::usb::{Driver, Instance};
use embassy_stm32::{bind_interrupts, peripherals, usb, Config};
use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
use embassy_usb::driver::EndpointError;
use embassy_usb::Builder;
use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
OTG_HS => usb::InterruptHandler<peripherals::USB_OTG_HS>;
});
// If you are trying this and your USB device doesn't connect, the most
// common issues are the RCC config and vbus_detection
//
// See https://embassy.dev/book/#_the_usb_examples_are_not_working_on_my_board_is_there_anything_else_i_need_to_configure
// for more information.
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
info!("Hello World!");
let mut config = Config::default();
{
use embassy_stm32::rcc::*;
config.rcc.hse = Some(Hse {
freq: Hertz(24_000_000),
mode: HseMode::Oscillator,
});
config.rcc.pll1 = Some(Pll {
source: PllSource::HSE,
prediv: PllPreDiv::DIV12,
mul: PllMul::MUL300,
divp: Some(PllDiv::DIV1), //600 MHz
divq: Some(PllDiv::DIV2), // 300 MHz
divr: Some(PllDiv::DIV2), // 300 MHz
});
config.rcc.sys = Sysclk::PLL1_P; // 600 MHz
config.rcc.ahb_pre = AHBPrescaler::DIV2; // 300 MHz
config.rcc.apb1_pre = APBPrescaler::DIV2; // 150 MHz
config.rcc.apb2_pre = APBPrescaler::DIV2; // 150 MHz
config.rcc.apb4_pre = APBPrescaler::DIV2; // 150 MHz
config.rcc.apb5_pre = APBPrescaler::DIV2; // 150 MHz
config.rcc.voltage_scale = VoltageScale::HIGH;
config.rcc.mux.usbphycsel = mux::Usbphycsel::HSE;
}
let p = embassy_stm32::init(config);
// Create the driver, from the HAL.
let mut ep_out_buffer = [0u8; 256];
let mut config = embassy_stm32::usb::Config::default();
// Do not enable vbus_detection. This is a safe default that works in all boards.
// However, if your USB device is self-powered (can stay powered on if USB is unplugged), you need
// to enable vbus_detection to comply with the USB spec. If you enable it, the board
// has to support it or USB won't work at all. See docs on `vbus_detection` for details.
config.vbus_detection = false;
let driver = Driver::new_hs(p.USB_OTG_HS, Irqs, p.PM6, p.PM5, &mut ep_out_buffer, config);
// Create embassy-usb Config
let mut config = embassy_usb::Config::new(0xc0de, 0xcafe);
config.manufacturer = Some("Embassy");
config.product = Some("USB-serial example");
config.serial_number = Some("12345678");
// Required for windows compatibility.
// https://developer.nordicsemi.com/nRF_Connect_SDK/doc/1.9.1/kconfig/CONFIG_CDC_ACM_IAD.html#help
config.device_class = 0xEF;
config.device_sub_class = 0x02;
config.device_protocol = 0x01;
config.composite_with_iads = true;
// Create embassy-usb DeviceBuilder using the driver and config.
// It needs some buffers for building the descriptors.
let mut config_descriptor = [0; 256];
let mut bos_descriptor = [0; 256];
let mut control_buf = [0; 64];
let mut state = State::new();
let mut builder = Builder::new(
driver,
config,
&mut config_descriptor,
&mut bos_descriptor,
&mut [], // no msos descriptors
&mut control_buf,
);
// Create classes on the builder.
let mut class = CdcAcmClass::new(&mut builder, &mut state, 64);
// Build the builder.
let mut usb = builder.build();
// Run the USB device.
let usb_fut = usb.run();
// Do stuff with the class!
let echo_fut = async {
loop {
class.wait_connection().await;
info!("Connected");
let _ = echo(&mut class).await;
info!("Disconnected");
}
};
// Run everything concurrently.
// If we had made everything `'static` above instead, we could do this using separate tasks instead.
join(usb_fut, echo_fut).await;
}
struct Disconnected {}
impl From<EndpointError> for Disconnected {
fn from(val: EndpointError) -> Self {
match val {
EndpointError::BufferOverflow => panic!("Buffer overflow"),
EndpointError::Disabled => Disconnected {},
}
}
}
async fn echo<'d, T: Instance + 'd>(class: &mut CdcAcmClass<'d, Driver<'d, T>>) -> Result<(), Disconnected> {
let mut buf = [0; 64];
loop {
let n = class.read_packet(&mut buf).await?;
let data = &buf[..n];
info!("data: {:x}", data);
class.write_packet(data).await?;
}
}