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https://github.com/embassy-rs/embassy.git
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Merge pull request #2652 from timokroeger/stm32-ucpd
STM32 USB Type-C/USB Power Delivery Interface (UCPD)
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
963fda2404
@ -764,6 +764,8 @@ fn main() {
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#[rustfmt::skip]
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let signals: HashMap<_, _> = [
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// (kind, signal) => trait
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(("ucpd", "CC1"), quote!(crate::ucpd::Cc1Pin)),
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(("ucpd", "CC2"), quote!(crate::ucpd::Cc2Pin)),
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(("usart", "TX"), quote!(crate::usart::TxPin)),
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(("usart", "RX"), quote!(crate::usart::RxPin)),
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(("usart", "CTS"), quote!(crate::usart::CtsPin)),
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@ -1102,6 +1104,8 @@ fn main() {
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let signals: HashMap<_, _> = [
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// (kind, signal) => trait
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(("ucpd", "RX"), quote!(crate::ucpd::RxDma)),
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(("ucpd", "TX"), quote!(crate::ucpd::TxDma)),
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(("usart", "RX"), quote!(crate::usart::RxDma)),
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(("usart", "TX"), quote!(crate::usart::TxDma)),
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(("lpuart", "RX"), quote!(crate::usart::RxDma)),
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@ -73,6 +73,8 @@ pub mod sai;
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pub mod sdmmc;
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#[cfg(spi)]
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pub mod spi;
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#[cfg(ucpd)]
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pub mod ucpd;
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#[cfg(uid)]
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pub mod uid;
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#[cfg(usart)]
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@ -281,9 +283,8 @@ pub fn init(config: Config) -> Peripherals {
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}
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unsafe {
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// TODO: refactor into mod ucpd
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#[cfg(ucpd)]
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ucpd_init(
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ucpd::init(
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cs,
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#[cfg(peri_ucpd1)]
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config.enable_ucpd1_dead_battery,
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@ -332,41 +333,3 @@ pub fn init(config: Config) -> Peripherals {
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p
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})
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}
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#[cfg(ucpd)]
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/// Safety: must only be called when all UCPDs are disabled (e.g. at startup)
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unsafe fn ucpd_init(
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_cs: critical_section::CriticalSection,
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#[cfg(peri_ucpd1)] ucpd1_db_enable: bool,
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#[cfg(peri_ucpd2)] ucpd2_db_enable: bool,
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) {
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#[cfg(stm32g0x1)]
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{
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// according to RM0444 (STM32G0x1) section 8.1.1:
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// when UCPD is disabled setting the strobe will disable dead battery
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// (which is enabled after reset) but if UCPD is enabled, setting the
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// strobe will apply the CC pin configuration from the control register
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// (which is why we need to be careful about when we call this)
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crate::pac::SYSCFG.cfgr1().modify(|w| {
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w.set_ucpd1_strobe(ucpd1_db_enable);
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w.set_ucpd2_strobe(ucpd2_db_enable);
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});
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}
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#[cfg(any(stm32g4, stm32l5))]
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{
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crate::pac::PWR.cr3().modify(|w| {
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#[cfg(stm32g4)]
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w.set_ucpd1_dbdis(!ucpd1_db_enable);
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#[cfg(stm32l5)]
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w.set_ucpd_dbdis(!ucpd1_db_enable);
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})
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}
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#[cfg(any(stm32h5, stm32u5))]
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{
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crate::pac::PWR.ucpdr().modify(|w| {
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w.set_ucpd_dbdis(!ucpd1_db_enable);
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})
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}
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}
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609
embassy-stm32/src/ucpd.rs
Normal file
609
embassy-stm32/src/ucpd.rs
Normal file
@ -0,0 +1,609 @@
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//! USB Type-C/USB Power Delivery Interface (UCPD)
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// Implementation Notes
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//
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// As of Feb. 2024 the UCPD peripheral is availalbe on: G0, G4, H5, L5, U5
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//
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// Cube HAL LL Driver (g0):
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// https://github.com/STMicroelectronics/stm32g0xx_hal_driver/blob/v1.4.6/Inc/stm32g0xx_ll_ucpd.h
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// https://github.com/STMicroelectronics/stm32g0xx_hal_driver/blob/v1.4.6/Src/stm32g0xx_ll_ucpd.c
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// Except for a the `LL_UCPD_RxAnalogFilterEnable/Disable()` functions the Cube HAL implementation of
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// all families is the same.
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//
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// Dead battery pull-down resistors functionality is enabled by default on startup and must
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// be disabled by setting a bit in PWR/SYSCFG registers. The exact name and location for that
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// bit is different for each familily.
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::sync::atomic::Ordering;
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use core::task::Poll;
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use embassy_hal_internal::drop::OnDrop;
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use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
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use crate::dma::{AnyChannel, Request, Transfer, TransferOptions};
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use crate::interrupt;
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use crate::interrupt::typelevel::Interrupt;
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use crate::pac::ucpd::vals::{Anamode, Ccenable, PscUsbpdclk, Txmode};
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pub use crate::pac::ucpd::vals::{Phyccsel as CcSel, TypecVstateCc as CcVState};
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use crate::rcc::RccPeripheral;
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pub(crate) fn init(
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_cs: critical_section::CriticalSection,
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#[cfg(peri_ucpd1)] ucpd1_db_enable: bool,
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#[cfg(peri_ucpd2)] ucpd2_db_enable: bool,
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) {
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#[cfg(stm32g0x1)]
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{
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// according to RM0444 (STM32G0x1) section 8.1.1:
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// when UCPD is disabled setting the strobe will disable dead battery
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// (which is enabled after reset) but if UCPD is enabled, setting the
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// strobe will apply the CC pin configuration from the control register
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// (which is why we need to be careful about when we call this)
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crate::pac::SYSCFG.cfgr1().modify(|w| {
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w.set_ucpd1_strobe(ucpd1_db_enable);
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w.set_ucpd2_strobe(ucpd2_db_enable);
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});
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}
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#[cfg(any(stm32g4, stm32l5))]
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{
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crate::pac::PWR.cr3().modify(|w| {
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#[cfg(stm32g4)]
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w.set_ucpd1_dbdis(!ucpd1_db_enable);
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#[cfg(stm32l5)]
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w.set_ucpd_dbdis(!ucpd1_db_enable);
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})
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}
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#[cfg(any(stm32h5, stm32u5))]
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{
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crate::pac::PWR.ucpdr().modify(|w| {
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w.set_ucpd_dbdis(!ucpd1_db_enable);
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})
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}
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}
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/// Pull-up or Pull-down resistor state of both CC lines.
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#[derive(Debug, Clone, Copy, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum CcPull {
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/// Analog PHY for CC pin disabled.
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Disabled,
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/// Rd=5.1k pull-down resistor.
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Sink,
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/// Rp=56k pull-up resistor to indicate default USB power.
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SourceDefaultUsb,
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/// Rp=22k pull-up resistor to indicate support for up to 1.5A.
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Source1_5A,
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/// Rp=10k pull-up resistor to indicate support for up to 3.0A.
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Source3_0A,
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}
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/// UCPD driver.
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pub struct Ucpd<'d, T: Instance> {
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cc_phy: CcPhy<'d, T>,
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}
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impl<'d, T: Instance> Ucpd<'d, T> {
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/// Creates a new UCPD driver instance.
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pub fn new(
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_peri: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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cc1: impl Peripheral<P = impl Cc1Pin<T>> + 'd,
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cc2: impl Peripheral<P = impl Cc2Pin<T>> + 'd,
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) -> Self {
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into_ref!(cc1, cc2);
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cc1.set_as_analog();
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cc2.set_as_analog();
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T::enable_and_reset();
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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let r = T::REGS;
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r.cfgr1().write(|w| {
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// "The receiver is designed to work in the clock frequency range from 6 to 18 MHz.
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// However, the optimum performance is ensured in the range from 6 to 12 MHz"
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// UCPD is driven by HSI16 (16MHz internal oscillator), which we need to divide by 2.
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w.set_psc_usbpdclk(PscUsbpdclk::DIV2);
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// Prescaler to produce a target half-bit frequency of 600kHz which is required
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// to produce transmit with a nominal nominal bit rate of 300Kbps+-10% using
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// biphase mark coding (BMC, aka differential manchester coding).
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// A divider of 13 gives the target frequency closest to spec (~615kHz, 1.625us).
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w.set_hbitclkdiv(13 - 1);
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// Time window for detecting non-idle (12-20us).
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// 1.75us * 8 = 14us.
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w.set_transwin(8 - 1);
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// Time from the end of last bit of a Frame until the start of the first bit of the
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// next Preamble (min 25us).
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// 1.75us * 17 = ~30us
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w.set_ifrgap(17 - 1);
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// TODO: Currently only hard reset and SOP messages can be received.
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// UNDOCUMENTED: This register can only be written while UCPDEN=0 (found by testing).
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w.set_rxordseten(0b1001);
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// Enable DMA
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w.set_txdmaen(true);
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w.set_rxdmaen(true);
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w.set_ucpden(true);
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});
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Self {
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cc_phy: CcPhy { _lifetime: PhantomData },
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}
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}
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/// Returns the TypeC CC PHY.
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pub fn cc_phy(&mut self) -> &mut CcPhy<'d, T> {
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&mut self.cc_phy
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}
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/// Splits the UCPD driver into a TypeC PHY to control and monitor CC voltage
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/// and a Power Delivery (PD) PHY with receiver and transmitter.
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pub fn split_pd_phy(
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self,
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rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
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tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
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cc_sel: CcSel,
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) -> (CcPhy<'d, T>, PdPhy<'d, T>) {
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let r = T::REGS;
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// TODO: Currently only SOP messages are supported.
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r.tx_ordsetr().write(|w| w.set_txordset(0b10001_11000_11000_11000));
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// Enable the receiver on one of the two CC lines.
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r.cr().modify(|w| w.set_phyccsel(cc_sel));
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// Enable hard reset receive interrupt.
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r.imr().modify(|w| w.set_rxhrstdetie(true));
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// Both parts must be dropped before the peripheral can be disabled.
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T::state().drop_not_ready.store(true, Ordering::Relaxed);
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into_ref!(rx_dma, tx_dma);
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let rx_dma_req = rx_dma.request();
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let tx_dma_req = tx_dma.request();
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(
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self.cc_phy,
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PdPhy {
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_lifetime: PhantomData,
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rx_dma_ch: rx_dma.map_into(),
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rx_dma_req,
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tx_dma_ch: tx_dma.map_into(),
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tx_dma_req,
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},
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)
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}
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}
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/// Control and monitoring of TypeC CC pin functionailty.
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pub struct CcPhy<'d, T: Instance> {
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_lifetime: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance> Drop for CcPhy<'d, T> {
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fn drop(&mut self) {
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let r = T::REGS;
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r.cr().modify(|w| {
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w.set_cc1tcdis(true);
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w.set_cc2tcdis(true);
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w.set_ccenable(Ccenable::DISABLED);
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});
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// Check if the PdPhy part was dropped already.
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let drop_not_ready = &T::state().drop_not_ready;
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if drop_not_ready.load(Ordering::Relaxed) {
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drop_not_ready.store(true, Ordering::Relaxed);
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} else {
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r.cfgr1().write(|w| w.set_ucpden(false));
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T::disable();
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T::Interrupt::disable();
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}
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}
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}
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impl<'d, T: Instance> CcPhy<'d, T> {
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/// Sets the pull-up/pull-down resistor values exposed on the CC pins.
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pub fn set_pull(&mut self, cc_pull: CcPull) {
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T::REGS.cr().modify(|w| {
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w.set_anamode(if cc_pull == CcPull::Sink {
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Anamode::SINK
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} else {
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Anamode::SOURCE
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});
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w.set_anasubmode(match cc_pull {
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CcPull::SourceDefaultUsb => 1,
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CcPull::Source1_5A => 2,
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CcPull::Source3_0A => 3,
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_ => 0,
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});
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w.set_ccenable(if cc_pull == CcPull::Disabled {
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Ccenable::DISABLED
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} else {
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Ccenable::BOTH
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});
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});
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// Disable dead-battery pull-down resistors which are enabled by default on boot.
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critical_section::with(|cs| {
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init(
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cs,
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false,
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#[cfg(peri_ucpd2)]
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false,
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);
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});
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}
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/// Returns the current voltage level of CC1 and CC2 pin as tuple.
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///
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/// Interpretation of the voltage levels depends on the configured CC line
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/// pull-up/pull-down resistance.
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pub fn vstate(&self) -> (CcVState, CcVState) {
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let sr = T::REGS.sr().read();
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(sr.typec_vstate_cc1(), sr.typec_vstate_cc2())
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}
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/// Waits for a change in voltage state on either CC line.
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pub async fn wait_for_vstate_change(&self) -> (CcVState, CcVState) {
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let _on_drop = OnDrop::new(|| self.enable_cc_interrupts(false));
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let prev_vstate = self.vstate();
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poll_fn(|cx| {
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let vstate = self.vstate();
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if vstate != prev_vstate {
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Poll::Ready(vstate)
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} else {
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T::state().waker.register(cx.waker());
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self.enable_cc_interrupts(true);
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Poll::Pending
|
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}
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})
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.await
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}
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fn enable_cc_interrupts(&self, enable: bool) {
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T::REGS.imr().modify(|w| {
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w.set_typecevt1ie(enable);
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w.set_typecevt2ie(enable);
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});
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}
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}
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/// Receive Error.
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#[derive(Debug, Clone, Copy)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum RxError {
|
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/// Incorrect CRC or truncated message (a line becoming static before EOP is met).
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Crc,
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/// Provided buffer was too small for the received message.
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Overrun,
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/// Hard Reset received before or during reception.
|
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HardReset,
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}
|
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/// Transmit Error.
|
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#[derive(Debug, Clone, Copy)]
|
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
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pub enum TxError {
|
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/// Concurrent receive in progress or excessive noise on the line.
|
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Discarded,
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/// Hard Reset received before or during transmission.
|
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HardReset,
|
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}
|
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|
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/// Power Delivery (PD) PHY.
|
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pub struct PdPhy<'d, T: Instance> {
|
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_lifetime: PhantomData<&'d mut T>,
|
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rx_dma_ch: PeripheralRef<'d, AnyChannel>,
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rx_dma_req: Request,
|
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tx_dma_ch: PeripheralRef<'d, AnyChannel>,
|
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tx_dma_req: Request,
|
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}
|
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|
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impl<'d, T: Instance> Drop for PdPhy<'d, T> {
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fn drop(&mut self) {
|
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// Check if the Type-C part was dropped already.
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let drop_not_ready = &T::state().drop_not_ready;
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if drop_not_ready.load(Ordering::Relaxed) {
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drop_not_ready.store(true, Ordering::Relaxed);
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} else {
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T::REGS.cfgr1().write(|w| w.set_ucpden(false));
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T::disable();
|
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T::Interrupt::disable();
|
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}
|
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}
|
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}
|
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|
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impl<'d, T: Instance> PdPhy<'d, T> {
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/// Receives a PD message into the provided buffer.
|
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///
|
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/// Returns the number of received bytes or an error.
|
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pub async fn receive(&mut self, buf: &mut [u8]) -> Result<usize, RxError> {
|
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let r = T::REGS;
|
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|
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let dma = unsafe {
|
||||
Transfer::new_read(
|
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&self.rx_dma_ch,
|
||||
self.rx_dma_req,
|
||||
r.rxdr().as_ptr() as *mut u8,
|
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buf,
|
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TransferOptions::default(),
|
||||
)
|
||||
};
|
||||
|
||||
// Clear interrupt flags (possibly set from last receive).
|
||||
r.icr().write(|w| {
|
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w.set_rxorddetcf(true);
|
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w.set_rxovrcf(true);
|
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w.set_rxmsgendcf(true);
|
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});
|
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|
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r.cr().modify(|w| w.set_phyrxen(true));
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let _on_drop = OnDrop::new(|| {
|
||||
r.cr().modify(|w| w.set_phyrxen(false));
|
||||
self.enable_rx_interrupt(false);
|
||||
});
|
||||
|
||||
poll_fn(|cx| {
|
||||
let sr = r.sr().read();
|
||||
if sr.rxhrstdet() {
|
||||
// Clean and re-enable hard reset receive interrupt.
|
||||
r.icr().write(|w| w.set_rxhrstdetcf(true));
|
||||
r.imr().modify(|w| w.set_rxhrstdetie(true));
|
||||
Poll::Ready(Err(RxError::HardReset))
|
||||
} else if sr.rxmsgend() {
|
||||
let ret = if sr.rxovr() {
|
||||
Err(RxError::Overrun)
|
||||
} else if sr.rxerr() {
|
||||
Err(RxError::Crc)
|
||||
} else {
|
||||
Ok(())
|
||||
};
|
||||
Poll::Ready(ret)
|
||||
} else {
|
||||
T::state().waker.register(cx.waker());
|
||||
self.enable_rx_interrupt(true);
|
||||
Poll::Pending
|
||||
}
|
||||
})
|
||||
.await?;
|
||||
|
||||
// Make sure that the last byte was fetched by DMA.
|
||||
while r.sr().read().rxne() {
|
||||
if dma.get_remaining_transfers() == 0 {
|
||||
return Err(RxError::Overrun);
|
||||
}
|
||||
}
|
||||
|
||||
Ok(r.rx_payszr().read().rxpaysz().into())
|
||||
}
|
||||
|
||||
fn enable_rx_interrupt(&self, enable: bool) {
|
||||
T::REGS.imr().modify(|w| w.set_rxmsgendie(enable));
|
||||
}
|
||||
|
||||
/// Transmits a PD message.
|
||||
pub async fn transmit(&mut self, buf: &[u8]) -> Result<(), TxError> {
|
||||
let r = T::REGS;
|
||||
|
||||
// When a previous transmission was dropped before it had finished it
|
||||
// might still be running because there is no way to abort an ongoing
|
||||
// message transmission. Wait for it to finish but ignore errors.
|
||||
if r.cr().read().txsend() {
|
||||
if let Err(TxError::HardReset) = self.wait_tx_done().await {
|
||||
return Err(TxError::HardReset);
|
||||
}
|
||||
}
|
||||
|
||||
// Clear the TX interrupt flags.
|
||||
T::REGS.icr().write(|w| {
|
||||
w.set_txmsgdisccf(true);
|
||||
w.set_txmsgsentcf(true);
|
||||
});
|
||||
|
||||
// Start the DMA and let it do its thing in the background.
|
||||
let _dma = unsafe {
|
||||
Transfer::new_write(
|
||||
&self.tx_dma_ch,
|
||||
self.tx_dma_req,
|
||||
buf,
|
||||
r.txdr().as_ptr() as *mut u8,
|
||||
TransferOptions::default(),
|
||||
)
|
||||
};
|
||||
|
||||
// Configure and start the transmission.
|
||||
r.tx_payszr().write(|w| w.set_txpaysz(buf.len() as _));
|
||||
r.cr().modify(|w| {
|
||||
w.set_txmode(Txmode::PACKET);
|
||||
w.set_txsend(true);
|
||||
});
|
||||
|
||||
self.wait_tx_done().await
|
||||
}
|
||||
|
||||
async fn wait_tx_done(&self) -> Result<(), TxError> {
|
||||
let _on_drop = OnDrop::new(|| self.enable_tx_interrupts(false));
|
||||
poll_fn(|cx| {
|
||||
let r = T::REGS;
|
||||
let sr = r.sr().read();
|
||||
if sr.rxhrstdet() {
|
||||
// Clean and re-enable hard reset receive interrupt.
|
||||
r.icr().write(|w| w.set_rxhrstdetcf(true));
|
||||
r.imr().modify(|w| w.set_rxhrstdetie(true));
|
||||
Poll::Ready(Err(TxError::HardReset))
|
||||
} else if sr.txmsgdisc() {
|
||||
Poll::Ready(Err(TxError::Discarded))
|
||||
} else if sr.txmsgsent() {
|
||||
Poll::Ready(Ok(()))
|
||||
} else {
|
||||
T::state().waker.register(cx.waker());
|
||||
self.enable_tx_interrupts(true);
|
||||
Poll::Pending
|
||||
}
|
||||
})
|
||||
.await
|
||||
}
|
||||
|
||||
fn enable_tx_interrupts(&self, enable: bool) {
|
||||
T::REGS.imr().modify(|w| {
|
||||
w.set_txmsgdiscie(enable);
|
||||
w.set_txmsgsentie(enable);
|
||||
});
|
||||
}
|
||||
|
||||
/// Transmit a hard reset.
|
||||
pub async fn transmit_hardreset(&mut self) -> Result<(), TxError> {
|
||||
let r = T::REGS;
|
||||
|
||||
// Clear the hardreset interrupt flags.
|
||||
T::REGS.icr().write(|w| {
|
||||
w.set_hrstdisccf(true);
|
||||
w.set_hrstsentcf(true);
|
||||
});
|
||||
|
||||
// Trigger hard reset transmission.
|
||||
r.cr().modify(|w| {
|
||||
w.set_txhrst(true);
|
||||
});
|
||||
|
||||
let _on_drop = OnDrop::new(|| self.enable_hardreset_interrupts(false));
|
||||
poll_fn(|cx| {
|
||||
let r = T::REGS;
|
||||
let sr = r.sr().read();
|
||||
if sr.rxhrstdet() {
|
||||
// Clean and re-enable hard reset receive interrupt.
|
||||
r.icr().write(|w| w.set_rxhrstdetcf(true));
|
||||
r.imr().modify(|w| w.set_rxhrstdetie(true));
|
||||
Poll::Ready(Err(TxError::HardReset))
|
||||
} else if sr.hrstdisc() {
|
||||
Poll::Ready(Err(TxError::Discarded))
|
||||
} else if sr.hrstsent() {
|
||||
Poll::Ready(Ok(()))
|
||||
} else {
|
||||
T::state().waker.register(cx.waker());
|
||||
self.enable_hardreset_interrupts(true);
|
||||
Poll::Pending
|
||||
}
|
||||
})
|
||||
.await
|
||||
}
|
||||
|
||||
fn enable_hardreset_interrupts(&self, enable: bool) {
|
||||
T::REGS.imr().modify(|w| {
|
||||
w.set_hrstdiscie(enable);
|
||||
w.set_hrstsentie(enable);
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
/// Interrupt handler.
|
||||
pub struct InterruptHandler<T: Instance> {
|
||||
_phantom: PhantomData<T>,
|
||||
}
|
||||
|
||||
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
|
||||
unsafe fn on_interrupt() {
|
||||
let r = T::REGS;
|
||||
let sr = r.sr().read();
|
||||
|
||||
if sr.typecevt1() || sr.typecevt2() {
|
||||
r.icr().write(|w| {
|
||||
w.set_typecevt1cf(true);
|
||||
w.set_typecevt2cf(true);
|
||||
});
|
||||
}
|
||||
|
||||
if sr.rxhrstdet() {
|
||||
r.imr().modify(|w| w.set_rxhrstdetie(false));
|
||||
}
|
||||
|
||||
if sr.rxmsgend() {
|
||||
r.imr().modify(|w| w.set_rxmsgendie(false));
|
||||
}
|
||||
|
||||
if sr.txmsgdisc() || sr.txmsgsent() {
|
||||
r.imr().modify(|w| {
|
||||
w.set_txmsgdiscie(false);
|
||||
w.set_txmsgsentie(false);
|
||||
});
|
||||
}
|
||||
|
||||
if sr.hrstdisc() || sr.hrstsent() {
|
||||
r.imr().modify(|w| {
|
||||
w.set_hrstdiscie(false);
|
||||
w.set_hrstsentie(false);
|
||||
});
|
||||
}
|
||||
|
||||
// Wake the task to clear and re-enabled interrupts.
|
||||
T::state().waker.wake();
|
||||
}
|
||||
}
|
||||
|
||||
/// UCPD instance trait.
|
||||
pub trait Instance: sealed::Instance + RccPeripheral {}
|
||||
|
||||
mod sealed {
|
||||
use core::sync::atomic::AtomicBool;
|
||||
|
||||
use embassy_sync::waitqueue::AtomicWaker;
|
||||
|
||||
pub struct State {
|
||||
pub waker: AtomicWaker,
|
||||
// Inverted logic for a default state of 0 so that the data goes into the .bss section.
|
||||
pub drop_not_ready: AtomicBool,
|
||||
}
|
||||
|
||||
impl State {
|
||||
pub const fn new() -> Self {
|
||||
Self {
|
||||
waker: AtomicWaker::new(),
|
||||
drop_not_ready: AtomicBool::new(false),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub trait Instance {
|
||||
type Interrupt: crate::interrupt::typelevel::Interrupt;
|
||||
const REGS: crate::pac::ucpd::Ucpd;
|
||||
fn state() -> &'static crate::ucpd::sealed::State;
|
||||
}
|
||||
}
|
||||
|
||||
foreach_interrupt!(
|
||||
($inst:ident, ucpd, UCPD, GLOBAL, $irq:ident) => {
|
||||
impl sealed::Instance for crate::peripherals::$inst {
|
||||
type Interrupt = crate::interrupt::typelevel::$irq;
|
||||
|
||||
const REGS: crate::pac::ucpd::Ucpd = crate::pac::$inst;
|
||||
|
||||
fn state() -> &'static crate::ucpd::sealed::State {
|
||||
static STATE: crate::ucpd::sealed::State = crate::ucpd::sealed::State::new();
|
||||
&STATE
|
||||
}
|
||||
}
|
||||
|
||||
impl Instance for crate::peripherals::$inst {}
|
||||
};
|
||||
);
|
||||
|
||||
pin_trait!(Cc1Pin, Instance);
|
||||
pin_trait!(Cc2Pin, Instance);
|
||||
|
||||
dma_trait!(TxDma, Instance);
|
||||
dma_trait!(RxDma, Instance);
|
||||
86
examples/stm32g4/src/bin/usb_c_pd.rs
Normal file
86
examples/stm32g4/src/bin/usb_c_pd.rs
Normal file
@ -0,0 +1,86 @@
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
|
||||
use defmt::{error, info, Format};
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::ucpd::{self, CcPhy, CcPull, CcSel, CcVState, Ucpd};
|
||||
use embassy_stm32::{bind_interrupts, peripherals, Config};
|
||||
use embassy_time::{with_timeout, Duration};
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
bind_interrupts!(struct Irqs {
|
||||
UCPD1 => ucpd::InterruptHandler<peripherals::UCPD1>;
|
||||
});
|
||||
|
||||
#[derive(Debug, Format)]
|
||||
enum CableOrientation {
|
||||
Normal,
|
||||
Flipped,
|
||||
DebugAccessoryMode,
|
||||
}
|
||||
|
||||
// Returns true when the cable
|
||||
async fn wait_attached<T: ucpd::Instance>(cc_phy: &mut CcPhy<'_, T>) -> CableOrientation {
|
||||
loop {
|
||||
let (cc1, cc2) = cc_phy.vstate();
|
||||
if cc1 == CcVState::LOWEST && cc2 == CcVState::LOWEST {
|
||||
// Detached, wait until attached by monitoring the CC lines.
|
||||
cc_phy.wait_for_vstate_change().await;
|
||||
continue;
|
||||
}
|
||||
|
||||
// Attached, wait for CC lines to be stable for tCCDebounce (100..200ms).
|
||||
if with_timeout(Duration::from_millis(100), cc_phy.wait_for_vstate_change())
|
||||
.await
|
||||
.is_ok()
|
||||
{
|
||||
// State has changed, restart detection procedure.
|
||||
continue;
|
||||
};
|
||||
|
||||
// State was stable for the complete debounce period, check orientation.
|
||||
return match (cc1, cc2) {
|
||||
(_, CcVState::LOWEST) => CableOrientation::Normal, // CC1 connected
|
||||
(CcVState::LOWEST, _) => CableOrientation::Flipped, // CC2 connected
|
||||
_ => CableOrientation::DebugAccessoryMode, // Both connected (special cable)
|
||||
};
|
||||
}
|
||||
}
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) {
|
||||
let mut config = Config::default();
|
||||
config.enable_ucpd1_dead_battery = true;
|
||||
let p = embassy_stm32::init(config);
|
||||
|
||||
info!("Hello World!");
|
||||
|
||||
let mut ucpd = Ucpd::new(p.UCPD1, Irqs {}, p.PB6, p.PB4);
|
||||
ucpd.cc_phy().set_pull(CcPull::Sink);
|
||||
|
||||
info!("Waiting for USB connection...");
|
||||
let cable_orientation = wait_attached(ucpd.cc_phy()).await;
|
||||
info!("USB cable connected, orientation: {}", cable_orientation);
|
||||
|
||||
let cc_sel = match cable_orientation {
|
||||
CableOrientation::Normal => {
|
||||
info!("Starting PD communication on CC1 pin");
|
||||
CcSel::CC1
|
||||
}
|
||||
CableOrientation::Flipped => {
|
||||
info!("Starting PD communication on CC2 pin");
|
||||
CcSel::CC2
|
||||
}
|
||||
CableOrientation::DebugAccessoryMode => panic!("No PD communication in DAM"),
|
||||
};
|
||||
let (_cc_phy, mut pd_phy) = ucpd.split_pd_phy(p.DMA1_CH1, p.DMA1_CH2, cc_sel);
|
||||
|
||||
loop {
|
||||
// Enough space for the longest non-extended data message.
|
||||
let mut buf = [0_u8; 30];
|
||||
match pd_phy.receive(buf.as_mut()).await {
|
||||
Ok(n) => info!("USB PD RX: {=[u8]:?}", &buf[..n]),
|
||||
Err(e) => error!("USB PD RX: {}", e),
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user