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https://github.com/embassy-rs/embassy.git
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Improve write_cmd parameters
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9005d26fca
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@ -123,7 +123,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
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}
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/// DCS or Generic short/long write command
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pub fn write_cmd(&mut self, channel_id: u8, params: &[u8]) {
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pub fn write_cmd(&mut self, channel_id: u8, params: &[u8]) -> Result<(), Error> {
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if params.len() <= 2 {
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self.short_write(channel_id, PacketType::DcsShortPktWriteP1, params[0], params[1])
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} else {
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@ -135,18 +135,26 @@ impl<'d, T: Instance> DsiHost<'d, T> {
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}
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}
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fn short_write(&mut self, channel_id: u8, packet_type: PacketType, param1: u8, param2: u8) {
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fn short_write(&mut self, channel_id: u8, packet_type: PacketType, param1: u8, param2: u8) -> Result<(), Error> {
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#[cfg(feature = "defmt")]
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defmt::debug!("short_write: BEGIN wait for command fifo empty");
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// Wait for Command FIFO empty
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self.wait_command_fifo_empty().unwrap();
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self.wait_command_fifo_empty()?;
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#[cfg(feature = "defmt")]
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defmt::debug!("short_write: END wait for command fifo empty");
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// Configure the packet to send a short DCS command with 0 or 1 parameters
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// Update the DSI packet header with new information
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self.config_packet_header(channel_id, packet_type, param1, param2);
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self.wait_command_fifo_empty()?;
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let status = T::regs().isr1().read().0;
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if status != 0 {
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error!("ISR1 after short_write(): {:b}", status);
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}
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Ok(())
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}
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fn config_packet_header(&mut self, channel_id: u8, packet_type: PacketType, param1: u8, param2: u8) {
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@ -161,7 +169,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
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/// Write long DCS or long Generic command.
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///
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/// `params` is expected to contain at least 3 elements. Use [`short_write`] for 2 or less.
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fn long_write(&mut self, channel_id: u8, packet_type: PacketType, params: &[u8]) {
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fn long_write(&mut self, channel_id: u8, packet_type: PacketType, params: &[u8]) -> Result<(), Error> {
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// Must be a long packet if we do the long write, obviously.
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assert!(matches!(
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packet_type,
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@ -174,7 +182,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
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#[cfg(feature = "defmt")]
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defmt::debug!("long_write: BEGIN wait for command fifo empty");
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self.wait_command_fifo_empty().unwrap();
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self.wait_command_fifo_empty()?;
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#[cfg(feature = "defmt")]
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defmt::debug!("long_write: DONE wait for command fifo empty");
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@ -198,8 +206,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
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w.set_data1(dcs_code);
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});
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// FIXME: This probably should return an error
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self.wait_command_fifo_empty().unwrap();
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self.wait_command_fifo_empty()?;
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// These steps are only necessary if more than 1x 4 bytes need to go into the FIFO
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if data.len() >= 4 {
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@ -210,6 +217,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
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// Keep filling the buffer with remaining data
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for param in iter {
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self.wait_command_fifo_not_full()?;
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T::regs().gpdr().write(|w| {
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w.set_data4(param[3]);
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w.set_data3(param[2]);
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@ -222,6 +230,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
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// If the remaining data was not devisible by 4 we get a remainder
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if remainder.len() >= 1 {
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self.wait_command_fifo_not_full()?;
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T::regs().gpdr().write(|w| {
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if let Some(x) = remainder.get(2) {
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w.set_data3(*x);
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@ -235,12 +244,20 @@ impl<'d, T: Instance> DsiHost<'d, T> {
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}
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}
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// Configure the packet to send a long DCS command
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T::regs().ghcr().write(|w| {
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w.set_dt(packet_type.into());
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w.set_vcid(channel_id);
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w.set_wclsb((params.len() & 0x00FF) as u8);
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w.set_wcmsb((params.len() & 0xFF00 >> 8) as u8);
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});
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self.config_packet_header(
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channel_id,
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packet_type,
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(params.len() & 0x00FF) as u8,
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((params.len() & 0xFF00) >> 8) as u8,
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);
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self.wait_command_fifo_empty()?;
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let status = T::regs().isr1().read().0;
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if status != 0 {
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error!("ISR1 after long_write(): {:b}", status);
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}
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Ok(())
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}
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/// Read DSI Register
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@ -273,9 +290,11 @@ impl<'d, T: Instance> DsiHost<'d, T> {
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_ => return Err(Error::InvalidPacketType),
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}
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self.wait_read_not_busy()?;
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// Obtain chunks of 32-bit so the entire FIFO data register can be read
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for bytes in data.chunks_exact_mut(4) {
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self.wait_payload_read_fifo_not_empty().unwrap();
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self.wait_payload_read_fifo_not_empty()?;
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// Only perform a single read on the entire register to avoid unintended side-effects
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let gpdr = T::regs().gpdr().read();
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@ -288,7 +307,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
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// Collect the remaining chunks and read the corresponding number of bytes from the FIFO
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let remainder = data.chunks_exact_mut(4).into_remainder();
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if !remainder.is_empty() {
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self.wait_payload_read_fifo_not_empty().unwrap();
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self.wait_payload_read_fifo_not_empty()?;
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// Only perform a single read on the entire register to avoid unintended side-effects
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let gpdr = T::regs().gpdr().read();
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if let Some(x) = remainder.get_mut(0) {
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