Merge pull request #2672 from nautd/karun/main_octospi_implementation

Octospi implementation

embassy-stm32/Cargo.toml

@@ -70,7 +70,8 @@ rand_core = "0.6.3"
 sdio-host = "0.5.0"
 critical-section = "1.1"
 #stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-f84633553331c2d154ee72de779a40cbb10fd1bd" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-2b7ec569a5510c324693f0515ac8ea20b12917a9" }
+
 vcell = "0.1.3"
 nb = "1.0.0"
 stm32-fmc = "0.3.0"
@@ -93,9 +94,9 @@ critical-section = { version = "1.1", features = ["std"] }
 [build-dependencies]
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
-#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-f84633553331c2d154ee72de779a40cbb10fd1bd", default-features = false, features = ["metadata"]}
 
+#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-2b7ec569a5510c324693f0515ac8ea20b12917a9", default-features = false, features = ["metadata"]}
 
 [features]
 default = ["rt"]

embassy-stm32/build.rs

@@ -1006,7 +1006,19 @@ fn main() {
         (("quadspi", "BK2_IO3"), quote!(crate::qspi::BK2D3Pin)),
         (("quadspi", "BK2_NCS"), quote!(crate::qspi::BK2NSSPin)),
         (("quadspi", "CLK"), quote!(crate::qspi::SckPin)),
-             ].into();
+        (("octospi", "IO0"), quote!(crate::ospi::D0Pin)),
+        (("octospi", "IO1"), quote!(crate::ospi::D1Pin)),
+        (("octospi", "IO2"), quote!(crate::ospi::D2Pin)),
+        (("octospi", "IO3"), quote!(crate::ospi::D3Pin)),
+        (("octospi", "IO4"), quote!(crate::ospi::D4Pin)),
+        (("octospi", "IO5"), quote!(crate::ospi::D5Pin)),
+        (("octospi", "IO6"), quote!(crate::ospi::D6Pin)),
+        (("octospi", "IO7"), quote!(crate::ospi::D7Pin)),
+        (("octospi", "DQS"), quote!(crate::ospi::DQSPin)),
+        (("octospi", "NCS"), quote!(crate::ospi::NSSPin)),
+        (("octospi", "CLK"), quote!(crate::ospi::SckPin)),
+        (("octospi", "NCLK"), quote!(crate::ospi::NckPin)),
+    ].into();
 
     for p in METADATA.peripherals {
         if let Some(regs) = &p.registers {
@@ -1129,6 +1141,7 @@ fn main() {
         // SDMMCv1 uses the same channel for both directions, so just implement for RX
         (("sdmmc", "RX"), quote!(crate::sdmmc::SdmmcDma)),
         (("quadspi", "QUADSPI"), quote!(crate::qspi::QuadDma)),
+        (("octospi", "OCTOSPI1"), quote!(crate::ospi::OctoDma)),
         (("dac", "CH1"), quote!(crate::dac::DacDma1)),
         (("dac", "CH2"), quote!(crate::dac::DacDma2)),
         (("timer", "UP"), quote!(crate::timer::UpDma)),

embassy-stm32/src/lib.rs

@@ -64,6 +64,8 @@ pub mod ipcc;
 pub mod low_power;
 #[cfg(opamp)]
 pub mod opamp;
+#[cfg(octospi)]
+pub mod ospi;
 #[cfg(quadspi)]
 pub mod qspi;
 #[cfg(rng)]

embassy-stm32/src/ospi/enums.rs

@@ -0,0 +1,386 @@
+//! Enums used in Ospi configuration.
+
+#[allow(dead_code)]
+#[derive(Copy, Clone)]
+pub(crate) enum OspiMode {
+    IndirectWrite,
+    IndirectRead,
+    AutoPolling,
+    MemoryMapped,
+}
+
+impl Into<u8> for OspiMode {
+    fn into(self) -> u8 {
+        match self {
+            OspiMode::IndirectWrite => 0b00,
+            OspiMode::IndirectRead => 0b01,
+            OspiMode::AutoPolling => 0b10,
+            OspiMode::MemoryMapped => 0b11,
+        }
+    }
+}
+
+/// Ospi lane width
+#[allow(dead_code)]
+#[derive(Copy, Clone)]
+pub enum OspiWidth {
+    /// None
+    NONE,
+    /// Single lane
+    SING,
+    /// Dual lanes
+    DUAL,
+    /// Quad lanes
+    QUAD,
+    /// Eight lanes
+    OCTO,
+}
+
+impl Into<u8> for OspiWidth {
+    fn into(self) -> u8 {
+        match self {
+            OspiWidth::NONE => 0b00,
+            OspiWidth::SING => 0b01,
+            OspiWidth::DUAL => 0b10,
+            OspiWidth::QUAD => 0b11,
+            OspiWidth::OCTO => 0b100,
+        }
+    }
+}
+
+/// Flash bank selection
+#[allow(dead_code)]
+#[derive(Copy, Clone)]
+pub enum FlashSelection {
+    /// Bank 1
+    Flash1,
+    /// Bank 2
+    Flash2,
+}
+
+impl Into<bool> for FlashSelection {
+    fn into(self) -> bool {
+        match self {
+            FlashSelection::Flash1 => false,
+            FlashSelection::Flash2 => true,
+        }
+    }
+}
+
+/// Wrap Size
+#[allow(dead_code)]
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum WrapSize {
+    None,
+    _16Bytes,
+    _32Bytes,
+    _64Bytes,
+    _128Bytes,
+}
+
+impl Into<u8> for WrapSize {
+    fn into(self) -> u8 {
+        match self {
+            WrapSize::None => 0x00,
+            WrapSize::_16Bytes => 0x02,
+            WrapSize::_32Bytes => 0x03,
+            WrapSize::_64Bytes => 0x04,
+            WrapSize::_128Bytes => 0x05,
+        }
+    }
+}
+
+/// Memory Type
+#[allow(missing_docs)]
+#[allow(dead_code)]
+#[derive(Copy, Clone)]
+pub enum MemoryType {
+    Micron,
+    Macronix,
+    Standard,
+    MacronixRam,
+    HyperBusMemory,
+    HyperBusRegister,
+}
+
+impl Into<u8> for MemoryType {
+    fn into(self) -> u8 {
+        match self {
+            MemoryType::Micron => 0x00,
+            MemoryType::Macronix => 0x01,
+            MemoryType::Standard => 0x02,
+            MemoryType::MacronixRam => 0x03,
+            MemoryType::HyperBusMemory => 0x04,
+            MemoryType::HyperBusRegister => 0x04,
+        }
+    }
+}
+
+/// Ospi memory size.
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum MemorySize {
+    _1KiB,
+    _2KiB,
+    _4KiB,
+    _8KiB,
+    _16KiB,
+    _32KiB,
+    _64KiB,
+    _128KiB,
+    _256KiB,
+    _512KiB,
+    _1MiB,
+    _2MiB,
+    _4MiB,
+    _8MiB,
+    _16MiB,
+    _32MiB,
+    _64MiB,
+    _128MiB,
+    _256MiB,
+    _512MiB,
+    _1GiB,
+    _2GiB,
+    _4GiB,
+    Other(u8),
+}
+
+impl Into<u8> for MemorySize {
+    fn into(self) -> u8 {
+        match self {
+            MemorySize::_1KiB => 9,
+            MemorySize::_2KiB => 10,
+            MemorySize::_4KiB => 11,
+            MemorySize::_8KiB => 12,
+            MemorySize::_16KiB => 13,
+            MemorySize::_32KiB => 14,
+            MemorySize::_64KiB => 15,
+            MemorySize::_128KiB => 16,
+            MemorySize::_256KiB => 17,
+            MemorySize::_512KiB => 18,
+            MemorySize::_1MiB => 19,
+            MemorySize::_2MiB => 20,
+            MemorySize::_4MiB => 21,
+            MemorySize::_8MiB => 22,
+            MemorySize::_16MiB => 23,
+            MemorySize::_32MiB => 24,
+            MemorySize::_64MiB => 25,
+            MemorySize::_128MiB => 26,
+            MemorySize::_256MiB => 27,
+            MemorySize::_512MiB => 28,
+            MemorySize::_1GiB => 29,
+            MemorySize::_2GiB => 30,
+            MemorySize::_4GiB => 31,
+            MemorySize::Other(val) => val,
+        }
+    }
+}
+
+/// Ospi Address size
+#[derive(Copy, Clone)]
+pub enum AddressSize {
+    /// 8-bit address
+    _8Bit,
+    /// 16-bit address
+    _16Bit,
+    /// 24-bit address
+    _24bit,
+    /// 32-bit address
+    _32bit,
+}
+
+impl Into<u8> for AddressSize {
+    fn into(self) -> u8 {
+        match self {
+            AddressSize::_8Bit => 0b00,
+            AddressSize::_16Bit => 0b01,
+            AddressSize::_24bit => 0b10,
+            AddressSize::_32bit => 0b11,
+        }
+    }
+}
+
+/// Time the Chip Select line stays high.
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum ChipSelectHighTime {
+    _1Cycle,
+    _2Cycle,
+    _3Cycle,
+    _4Cycle,
+    _5Cycle,
+    _6Cycle,
+    _7Cycle,
+    _8Cycle,
+}
+
+impl Into<u8> for ChipSelectHighTime {
+    fn into(self) -> u8 {
+        match self {
+            ChipSelectHighTime::_1Cycle => 0,
+            ChipSelectHighTime::_2Cycle => 1,
+            ChipSelectHighTime::_3Cycle => 2,
+            ChipSelectHighTime::_4Cycle => 3,
+            ChipSelectHighTime::_5Cycle => 4,
+            ChipSelectHighTime::_6Cycle => 5,
+            ChipSelectHighTime::_7Cycle => 6,
+            ChipSelectHighTime::_8Cycle => 7,
+        }
+    }
+}
+
+/// FIFO threshold.
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum FIFOThresholdLevel {
+    _1Bytes,
+    _2Bytes,
+    _3Bytes,
+    _4Bytes,
+    _5Bytes,
+    _6Bytes,
+    _7Bytes,
+    _8Bytes,
+    _9Bytes,
+    _10Bytes,
+    _11Bytes,
+    _12Bytes,
+    _13Bytes,
+    _14Bytes,
+    _15Bytes,
+    _16Bytes,
+    _17Bytes,
+    _18Bytes,
+    _19Bytes,
+    _20Bytes,
+    _21Bytes,
+    _22Bytes,
+    _23Bytes,
+    _24Bytes,
+    _25Bytes,
+    _26Bytes,
+    _27Bytes,
+    _28Bytes,
+    _29Bytes,
+    _30Bytes,
+    _31Bytes,
+    _32Bytes,
+}
+
+impl Into<u8> for FIFOThresholdLevel {
+    fn into(self) -> u8 {
+        match self {
+            FIFOThresholdLevel::_1Bytes => 0,
+            FIFOThresholdLevel::_2Bytes => 1,
+            FIFOThresholdLevel::_3Bytes => 2,
+            FIFOThresholdLevel::_4Bytes => 3,
+            FIFOThresholdLevel::_5Bytes => 4,
+            FIFOThresholdLevel::_6Bytes => 5,
+            FIFOThresholdLevel::_7Bytes => 6,
+            FIFOThresholdLevel::_8Bytes => 7,
+            FIFOThresholdLevel::_9Bytes => 8,
+            FIFOThresholdLevel::_10Bytes => 9,
+            FIFOThresholdLevel::_11Bytes => 10,
+            FIFOThresholdLevel::_12Bytes => 11,
+            FIFOThresholdLevel::_13Bytes => 12,
+            FIFOThresholdLevel::_14Bytes => 13,
+            FIFOThresholdLevel::_15Bytes => 14,
+            FIFOThresholdLevel::_16Bytes => 15,
+            FIFOThresholdLevel::_17Bytes => 16,
+            FIFOThresholdLevel::_18Bytes => 17,
+            FIFOThresholdLevel::_19Bytes => 18,
+            FIFOThresholdLevel::_20Bytes => 19,
+            FIFOThresholdLevel::_21Bytes => 20,
+            FIFOThresholdLevel::_22Bytes => 21,
+            FIFOThresholdLevel::_23Bytes => 22,
+            FIFOThresholdLevel::_24Bytes => 23,
+            FIFOThresholdLevel::_25Bytes => 24,
+            FIFOThresholdLevel::_26Bytes => 25,
+            FIFOThresholdLevel::_27Bytes => 26,
+            FIFOThresholdLevel::_28Bytes => 27,
+            FIFOThresholdLevel::_29Bytes => 28,
+            FIFOThresholdLevel::_30Bytes => 29,
+            FIFOThresholdLevel::_31Bytes => 30,
+            FIFOThresholdLevel::_32Bytes => 31,
+        }
+    }
+}
+
+/// Dummy cycle count
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum DummyCycles {
+    _0,
+    _1,
+    _2,
+    _3,
+    _4,
+    _5,
+    _6,
+    _7,
+    _8,
+    _9,
+    _10,
+    _11,
+    _12,
+    _13,
+    _14,
+    _15,
+    _16,
+    _17,
+    _18,
+    _19,
+    _20,
+    _21,
+    _22,
+    _23,
+    _24,
+    _25,
+    _26,
+    _27,
+    _28,
+    _29,
+    _30,
+    _31,
+}
+
+impl Into<u8> for DummyCycles {
+    fn into(self) -> u8 {
+        match self {
+            DummyCycles::_0 => 0,
+            DummyCycles::_1 => 1,
+            DummyCycles::_2 => 2,
+            DummyCycles::_3 => 3,
+            DummyCycles::_4 => 4,
+            DummyCycles::_5 => 5,
+            DummyCycles::_6 => 6,
+            DummyCycles::_7 => 7,
+            DummyCycles::_8 => 8,
+            DummyCycles::_9 => 9,
+            DummyCycles::_10 => 10,
+            DummyCycles::_11 => 11,
+            DummyCycles::_12 => 12,
+            DummyCycles::_13 => 13,
+            DummyCycles::_14 => 14,
+            DummyCycles::_15 => 15,
+            DummyCycles::_16 => 16,
+            DummyCycles::_17 => 17,
+            DummyCycles::_18 => 18,
+            DummyCycles::_19 => 19,
+            DummyCycles::_20 => 20,
+            DummyCycles::_21 => 21,
+            DummyCycles::_22 => 22,
+            DummyCycles::_23 => 23,
+            DummyCycles::_24 => 24,
+            DummyCycles::_25 => 25,
+            DummyCycles::_26 => 26,
+            DummyCycles::_27 => 27,
+            DummyCycles::_28 => 28,
+            DummyCycles::_29 => 29,
+            DummyCycles::_30 => 30,
+            DummyCycles::_31 => 31,
+        }
+    }
+}