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Merge pull request #3008 from aurelj/stm32-rcc-hsi

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stm32: ensure the core runs on HSI clock while setting up rcc
This commit is contained in:
Dario Nieuwenhuis 2024-05-27 17:28:13 +00:00 committed by GitHub
commit 8d7c3f7de1
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GPG Key ID: B5690EEEBB952194
5 changed files with 95 additions and 56 deletions
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44
embassy-stm32/src/rcc/c0.rs
View File

@ -76,25 +76,29 @@ impl Default for Config {
}
pub(crate) unsafe fn init(config: Config) {
// Turn on the HSI
match config.hsi {
None => RCC.cr().modify(|w| w.set_hsion(true)),
Some(hsi) => RCC.cr().modify(|w| {
w.set_hsidiv(hsi.sys_div);
w.set_hsikerdiv(hsi.ker_div);
w.set_hsion(true);
}),
}
while !RCC.cr().read().hsirdy() {}
// Use the HSI clock as system clock during the actual clock setup
RCC.cfgr().modify(|w| w.set_sw(Sysclk::HSISYS));
while RCC.cfgr().read().sws() != Sysclk::HSISYS {}
// Configure HSI
let (hsi, hsisys, hsiker) = match config.hsi {
None => {
RCC.cr().modify(|w| w.set_hsion(false));
(None, None, None)
}
Some(hsi) => {
RCC.cr().modify(|w| {
w.set_hsidiv(hsi.sys_div);
w.set_hsikerdiv(hsi.ker_div);
w.set_hsion(true);
});
while !RCC.cr().read().hsirdy() {}
(
Some(HSI_FREQ),
Some(HSI_FREQ / hsi.sys_div),
Some(HSI_FREQ / hsi.ker_div),
)
}
None => (None, None, None),
Some(hsi) => (
Some(HSI_FREQ),
Some(HSI_FREQ / hsi.sys_div),
Some(HSI_FREQ / hsi.ker_div),
),
};
// Configure HSE
@ -150,6 +154,12 @@ pub(crate) unsafe fn init(config: Config) {
w.set_hpre(config.ahb_pre);
w.set_ppre(config.apb1_pre);
});
while RCC.cfgr().read().sws() != config.sys {}
// Disable HSI if not used
if config.hsi.is_none() {
RCC.cr().modify(|w| w.set_hsion(false));
}
let rtc = config.ls.init();

24
embassy-stm32/src/rcc/f013.rs
View File

@ -135,17 +135,18 @@ impl Default for Config {
/// Initialize and Set the clock frequencies
pub(crate) unsafe fn init(config: Config) {
// Turn on the HSI
RCC.cr().modify(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
// Use the HSI clock as system clock during the actual clock setup
RCC.cfgr().modify(|w| w.set_sw(Sysclk::HSI));
while RCC.cfgr().read().sws() != Sysclk::HSI {}
// Configure HSI
let hsi = match config.hsi {
false => {
RCC.cr().modify(|w| w.set_hsion(false));
None
}
true => {
RCC.cr().modify(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
Some(HSI_FREQ)
}
false => None,
true => Some(HSI_FREQ),
};
// Configure HSE
@ -297,6 +298,11 @@ pub(crate) unsafe fn init(config: Config) {
RCC.cfgr().modify(|w| w.set_sw(config.sys));
while RCC.cfgr().read().sws() != config.sys {}
// Disable HSI if not used
if !config.hsi {
RCC.cr().modify(|w| w.set_hsion(false));
}
let rtc = config.ls.init();
// TODO: all this ADC stuff should probably go into the ADC module, not here.

25
embassy-stm32/src/rcc/g0.rs
View File

@ -116,17 +116,18 @@ pub struct PllFreq {
}
pub(crate) unsafe fn init(config: Config) {
// Turn on the HSI
RCC.cr().modify(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
// Use the HSI clock as system clock during the actual clock setup
RCC.cfgr().modify(|w| w.set_sw(Sysclk::HSI));
while RCC.cfgr().read().sws() != Sysclk::HSI {}
// Configure HSI
let hsi = match config.hsi {
false => {
RCC.cr().modify(|w| w.set_hsion(false));
None
}
true => {
RCC.cr().modify(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
Some(HSI_FREQ)
}
false => None,
true => Some(HSI_FREQ),
};
// Configure HSE
@ -259,6 +260,12 @@ pub(crate) unsafe fn init(config: Config) {
w.set_hpre(config.ahb_pre);
w.set_ppre(config.apb1_pre);
});
while RCC.cfgr().read().sws() != config.sys {}
// Disable HSI if not used
if !config.hsi {
RCC.cr().modify(|w| w.set_hsion(false));
}
if config.low_power_run {
assert!(sys <= Hertz(2_000_000));

25
embassy-stm32/src/rcc/g4.rs
View File

@ -117,17 +117,18 @@ pub struct PllFreq {
}
pub(crate) unsafe fn init(config: Config) {
// Turn on the HSI
RCC.cr().modify(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
// Use the HSI clock as system clock during the actual clock setup
RCC.cfgr().modify(|w| w.set_sw(Sysclk::HSI));
while RCC.cfgr().read().sws() != Sysclk::HSI {}
// Configure HSI
let hsi = match config.hsi {
false => {
RCC.cr().modify(|w| w.set_hsion(false));
None
}
true => {
RCC.cr().modify(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
Some(HSI_FREQ)
}
false => None,
true => Some(HSI_FREQ),
};
// Configure HSE
@ -285,6 +286,12 @@ pub(crate) unsafe fn init(config: Config) {
w.set_ppre1(config.apb1_pre);
w.set_ppre2(config.apb2_pre);
});
while RCC.cfgr().read().sws() != config.sys {}
// Disable HSI if not used
if !config.hsi {
RCC.cr().modify(|w| w.set_hsion(false));
}
if config.low_power_run {
assert!(sys <= Hertz(2_000_000));

33
embassy-stm32/src/rcc/h.rs
View File

@ -402,20 +402,24 @@ pub(crate) unsafe fn init(config: Config) {
}
}
// Turn on the HSI
match config.hsi {
None => RCC.cr().modify(|w| w.set_hsion(true)),
Some(hsidiv) => RCC.cr().modify(|w| {
w.set_hsidiv(hsidiv);
w.set_hsion(true);
}),
}
while !RCC.cr().read().hsirdy() {}
// Use the HSI clock as system clock during the actual clock setup
RCC.cfgr().modify(|w| w.set_sw(Sysclk::HSI));
while RCC.cfgr().read().sws() != Sysclk::HSI {}
// Configure HSI
let hsi = match config.hsi {
None => {
RCC.cr().modify(|w| w.set_hsion(false));
None
}
Some(hsidiv) => {
RCC.cr().modify(|w| {
w.set_hsidiv(hsidiv);
w.set_hsion(true);
});
while !RCC.cr().read().hsirdy() {}
Some(HSI_FREQ / hsidiv)
}
None => None,
Some(hsidiv) => Some(HSI_FREQ / hsidiv),
};
// Configure HSE
@ -608,6 +612,11 @@ pub(crate) unsafe fn init(config: Config) {
RCC.cfgr().modify(|w| w.set_sw(config.sys));
while RCC.cfgr().read().sws() != config.sys {}
// Disable HSI if not used
if config.hsi.is_none() {
RCC.cr().modify(|w| w.set_hsion(false));
}
// IO compensation cell - Requires CSI clock and SYSCFG
#[cfg(any(stm32h7))] // TODO h5, h7rs
if csi.is_some() {