mirror of
https://github.com/embassy-rs/embassy.git
synced 2024-11-25 00:02:28 +00:00
Fixing my git-based mistakes
This commit is contained in:
Caleb Jamison
Dario Nieuwenhuis
parent
8201979d71
commit
8900f5f52b
@ -3,11 +3,9 @@ use core::marker::PhantomData;
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use core::task::Poll;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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use pac::i2c;
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use super::{
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i2c_reserved_addr, AbortReason, Async, Blocking, Error, Instance, InterruptHandler, Mode, SclPin, SdaPin, FIFO_SIZE,
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};
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use crate::gpio::sealed::Pin;
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use crate::gpio::AnyPin;
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use crate::interrupt::typelevel::{Binding, Interrupt};
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@ -46,7 +44,6 @@ pub enum Error {
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#[non_exhaustive]
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#[derive(Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct Config {
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pub frequency: u32,
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}
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@ -307,6 +304,20 @@ impl<'d, T: Instance> I2c<'d, T, Async> {
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}
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}
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pub struct InterruptHandler<T: Instance> {
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_uart: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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// Mask interrupts and wake any task waiting for this interrupt
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unsafe fn on_interrupt() {
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let i2c = T::regs();
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i2c.ic_intr_mask().write_value(pac::i2c::regs::IcIntrMask::default());
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T::waker().wake();
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}
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}
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impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
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fn new_inner(
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_peri: impl Peripheral<P = T> + 'd,
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@ -729,8 +740,6 @@ mod nightly {
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}
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}
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}
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<<<<<<< HEAD:embassy-rp/src/i2c/i2c.rs
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=======
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pub fn i2c_reserved_addr(addr: u16) -> bool {
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((addr & 0x78) == 0 || (addr & 0x78) == 0x78) && addr != 0
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@ -1,311 +0,0 @@
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use core::future;
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use core::marker::PhantomData;
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use core::task::Poll;
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use embassy_hal_internal::into_ref;
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use pac::i2c;
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use super::{i2c_reserved_addr, AbortReason, Error, Instance, InterruptHandler, SclPin, SdaPin, FIFO_SIZE};
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use crate::interrupt::typelevel::{Binding, Interrupt};
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use crate::{pac, Peripheral};
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/// Received command
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Command {
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/// General Call
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GeneralCall(usize),
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/// Read
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Read,
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/// Write+read
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WriteRead(usize),
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/// Write
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Write(usize),
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}
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/// Possible responses to responding to a read
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum ReadStatus {
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/// Transaction Complete, controller naked our last byte
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Done,
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/// Transaction Incomplete, controller trying to read more bytes than were provided
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NeedMoreBytes,
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/// Transaction Complere, but controller stopped reading bytes before we ran out
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LeftoverBytes(u16),
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}
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/// Slave Configuration
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#[non_exhaustive]
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#[derive(Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct SlaveConfig {
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/// Target Address
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pub addr: u16,
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}
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impl Default for SlaveConfig {
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fn default() -> Self {
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Self { addr: 0x55 }
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}
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}
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pub struct I2cSlave<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance> I2cSlave<'d, T> {
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pub fn new(
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_peri: impl Peripheral<P = T> + 'd,
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scl: impl Peripheral<P = impl SclPin<T>> + 'd,
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sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
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_irq: impl Binding<T::Interrupt, InterruptHandler<T>>,
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config: SlaveConfig,
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) -> Self {
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into_ref!(_peri, scl, sda);
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assert!(!i2c_reserved_addr(config.addr));
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assert!(config.addr != 0);
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let p = T::regs();
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let reset = T::reset();
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crate::reset::reset(reset);
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crate::reset::unreset_wait(reset);
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p.ic_enable().write(|w| w.set_enable(false));
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p.ic_sar().write(|w| w.set_ic_sar(config.addr));
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p.ic_con().modify(|w| {
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w.set_master_mode(false);
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w.set_ic_slave_disable(false);
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w.set_tx_empty_ctrl(true);
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});
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// Set FIFO watermarks to 1 to make things simpler. This is encoded
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// by a register value of 0. Rx watermark should never change, but Tx watermark will be
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// adjusted in operation.
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p.ic_tx_tl().write(|w| w.set_tx_tl(0));
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p.ic_rx_tl().write(|w| w.set_rx_tl(0));
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// Configure SCL & SDA pins
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scl.gpio().ctrl().write(|w| w.set_funcsel(3));
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sda.gpio().ctrl().write(|w| w.set_funcsel(3));
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scl.pad_ctrl().write(|w| {
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w.set_schmitt(true);
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w.set_ie(true);
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w.set_od(false);
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w.set_pue(true);
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w.set_pde(false);
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});
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sda.pad_ctrl().write(|w| {
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w.set_schmitt(true);
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w.set_ie(true);
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w.set_od(false);
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w.set_pue(true);
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w.set_pde(false);
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});
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// Clear interrupts
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p.ic_clr_intr().read();
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// Enable I2C block
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p.ic_enable().write(|w| w.set_enable(true));
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// mask everything initially
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p.ic_intr_mask().write_value(i2c::regs::IcIntrMask(0));
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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Self { phantom: PhantomData }
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}
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/// Calls `f` to check if we are ready or not.
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/// If not, `g` is called once the waker is set (to eg enable the required interrupts).
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#[inline(always)]
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async fn wait_on<F, U, G>(&mut self, mut f: F, mut g: G) -> U
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where
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F: FnMut(&mut Self) -> Poll<U>,
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G: FnMut(&mut Self),
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{
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future::poll_fn(|cx| {
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let r = f(self);
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trace!("intr p: {:013b}", T::regs().ic_raw_intr_stat().read().0);
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if r.is_pending() {
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T::waker().register(cx.waker());
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g(self);
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}
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r
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})
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.await
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}
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#[inline(always)]
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fn drain_fifo(&mut self, buffer: &mut [u8], offset: usize) -> usize {
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let p = T::regs();
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let len = p.ic_rxflr().read().rxflr() as usize;
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let end = offset + len;
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for i in offset..end {
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buffer[i] = p.ic_data_cmd().read().dat();
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}
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end
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}
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#[inline(always)]
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fn write_to_fifo(&mut self, buffer: &[u8]) {
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let p = T::regs();
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for byte in buffer {
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p.ic_data_cmd().write(|w| w.set_dat(*byte));
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}
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}
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/// Wait asynchronously for commands from an I2C master.
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/// `buffer` is provided in case master does a 'write' and is unused for 'read'.
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pub async fn listen(&mut self, buffer: &mut [u8]) -> Result<Command, Error> {
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let p = T::regs();
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p.ic_clr_intr().read();
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// set rx fifo watermark to 1 byte
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p.ic_rx_tl().write(|w| w.set_rx_tl(0));
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let mut len = 0;
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let ret = self
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.wait_on(
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|me| {
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let stat = p.ic_raw_intr_stat().read();
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if p.ic_rxflr().read().rxflr() > 0 {
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len = me.drain_fifo(buffer, len);
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// we're recieving data, set rx fifo watermark to 12 bytes to reduce interrupt noise
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p.ic_rx_tl().write(|w| w.set_rx_tl(11));
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}
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if stat.restart_det() && stat.rd_req() {
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Poll::Ready(Ok(Command::WriteRead(len)))
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} else if stat.gen_call() && stat.stop_det() && len > 0 {
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Poll::Ready(Ok(Command::GeneralCall(len)))
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} else if stat.stop_det() {
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Poll::Ready(Ok(Command::Write(len)))
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} else if stat.rd_req() {
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Poll::Ready(Ok(Command::Read))
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} else {
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Poll::Pending
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}
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},
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|_me| {
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p.ic_intr_mask().modify(|w| {
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w.set_m_stop_det(true);
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w.set_m_restart_det(true);
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w.set_m_gen_call(true);
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w.set_m_rd_req(true);
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w.set_m_rx_full(true);
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});
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},
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)
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.await;
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p.ic_clr_intr().read();
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ret
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}
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/// Respond to an I2C master READ command, asynchronously.
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pub async fn respond_to_read(&mut self, buffer: &[u8]) -> Result<ReadStatus, Error> {
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let p = T::regs();
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let mut chunks = buffer.chunks(FIFO_SIZE as usize);
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let ret = self
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.wait_on(
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|me| {
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if let Err(abort_reason) = me.read_and_clear_abort_reason() {
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if let Error::Abort(AbortReason::TxNotEmpty(bytes)) = abort_reason {
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return Poll::Ready(Ok(ReadStatus::LeftoverBytes(bytes)));
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} else {
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return Poll::Ready(Err(abort_reason));
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}
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}
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if let Some(chunk) = chunks.next() {
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me.write_to_fifo(chunk);
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Poll::Pending
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} else {
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let stat = p.ic_raw_intr_stat().read();
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if stat.rx_done() && stat.stop_det() {
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Poll::Ready(Ok(ReadStatus::Done))
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} else if stat.rd_req() {
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Poll::Ready(Ok(ReadStatus::NeedMoreBytes))
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} else {
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Poll::Pending
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}
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}
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},
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|_me| {
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p.ic_intr_mask().modify(|w| {
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w.set_m_stop_det(true);
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w.set_m_rx_done(true);
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w.set_m_tx_empty(true);
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w.set_m_tx_abrt(true);
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})
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},
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)
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.await;
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p.ic_clr_intr().read();
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ret
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}
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/// Respond to reads with the fill byte until the controller stops asking
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pub async fn respond_till_stop(&mut self, fill: u8) -> Result<(), Error> {
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loop {
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match self.respond_to_read(&[fill]).await {
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Ok(ReadStatus::NeedMoreBytes) => (),
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Ok(_) => break Ok(()),
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Err(e) => break Err(e),
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}
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}
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}
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#[inline(always)]
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fn read_and_clear_abort_reason(&mut self) -> Result<(), Error> {
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let p = T::regs();
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let mut abort_reason = p.ic_tx_abrt_source().read();
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// Mask off fifo flush count
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let tx_flush_cnt = abort_reason.tx_flush_cnt();
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abort_reason.set_tx_flush_cnt(0);
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// Mask off master_dis
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abort_reason.set_abrt_master_dis(false);
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if abort_reason.0 != 0 {
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// Note clearing the abort flag also clears the reason, and this
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// instance of flag is clear-on-read! Note also the
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// IC_CLR_TX_ABRT register always reads as 0.
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p.ic_clr_tx_abrt().read();
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let reason = if abort_reason.abrt_7b_addr_noack()
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| abort_reason.abrt_10addr1_noack()
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| abort_reason.abrt_10addr2_noack()
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{
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AbortReason::NoAcknowledge
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} else if abort_reason.arb_lost() {
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AbortReason::ArbitrationLoss
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} else if abort_reason.abrt_slvflush_txfifo() {
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AbortReason::TxNotEmpty(tx_flush_cnt)
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} else {
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AbortReason::Other(abort_reason.0)
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};
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Err(Error::Abort(reason))
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} else {
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Ok(())
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}
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}
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}
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@ -1,175 +0,0 @@
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mod i2c;
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mod i2c_slave;
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use core::marker::PhantomData;
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use embassy_sync::waitqueue::AtomicWaker;
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pub use i2c::{Config, I2c};
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pub use i2c_slave::{Command, I2cSlave, ReadStatus, SlaveConfig};
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use crate::{interrupt, pac, peripherals};
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const FIFO_SIZE: u8 = 16;
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/// I2C error abort reason
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum AbortReason {
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/// A bus operation was not acknowledged, e.g. due to the addressed device
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/// not being available on the bus or the device not being ready to process
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/// requests at the moment
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NoAcknowledge,
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/// The arbitration was lost, e.g. electrical problems with the clock signal
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ArbitrationLoss,
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/// Transmit ended with data still in fifo
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TxNotEmpty(u16),
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Other(u32),
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}
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/// I2C error
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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/// I2C abort with error
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Abort(AbortReason),
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/// User passed in a read buffer that was 0 length
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InvalidReadBufferLength,
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/// User passed in a write buffer that was 0 length
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InvalidWriteBufferLength,
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/// Target i2c address is out of range
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AddressOutOfRange(u16),
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/// Target i2c address is reserved
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AddressReserved(u16),
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}
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pub struct InterruptHandler<T: Instance> {
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_uart: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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// Mask interrupts and wake any task waiting for this interrupt
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unsafe fn on_interrupt() {
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let i2c = T::regs();
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i2c.ic_intr_mask().write_value(pac::i2c::regs::IcIntrMask::default());
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T::waker().wake();
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}
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}
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fn i2c_reserved_addr(addr: u16) -> bool {
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((addr & 0x78) == 0 || (addr & 0x78) == 0x78) && addr != 0
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}
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mod sealed {
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use embassy_sync::waitqueue::AtomicWaker;
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use crate::interrupt;
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pub trait Instance {
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const TX_DREQ: u8;
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const RX_DREQ: u8;
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type Interrupt: interrupt::typelevel::Interrupt;
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fn regs() -> crate::pac::i2c::I2c;
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fn reset() -> crate::pac::resets::regs::Peripherals;
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fn waker() -> &'static AtomicWaker;
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}
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pub trait Mode {}
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pub trait SdaPin<T: Instance> {}
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pub trait SclPin<T: Instance> {}
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}
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pub trait Mode: sealed::Mode {}
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macro_rules! impl_mode {
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($name:ident) => {
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impl sealed::Mode for $name {}
|
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impl Mode for $name {}
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};
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}
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pub struct Blocking;
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pub struct Async;
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impl_mode!(Blocking);
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impl_mode!(Async);
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|
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pub trait Instance: sealed::Instance {}
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macro_rules! impl_instance {
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($type:ident, $irq:ident, $reset:ident, $tx_dreq:expr, $rx_dreq:expr) => {
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impl sealed::Instance for peripherals::$type {
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const TX_DREQ: u8 = $tx_dreq;
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const RX_DREQ: u8 = $rx_dreq;
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type Interrupt = crate::interrupt::typelevel::$irq;
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|
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#[inline]
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fn regs() -> pac::i2c::I2c {
|
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pac::$type
|
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}
|
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|
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#[inline]
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fn reset() -> pac::resets::regs::Peripherals {
|
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let mut ret = pac::resets::regs::Peripherals::default();
|
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ret.$reset(true);
|
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ret
|
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}
|
||||
|
||||
#[inline]
|
||||
fn waker() -> &'static AtomicWaker {
|
||||
static WAKER: AtomicWaker = AtomicWaker::new();
|
||||
|
||||
&WAKER
|
||||
}
|
||||
}
|
||||
impl Instance for peripherals::$type {}
|
||||
};
|
||||
}
|
||||
|
||||
impl_instance!(I2C0, I2C0_IRQ, set_i2c0, 32, 33);
|
||||
impl_instance!(I2C1, I2C1_IRQ, set_i2c1, 34, 35);
|
||||
|
||||
pub trait SdaPin<T: Instance>: sealed::SdaPin<T> + crate::gpio::Pin {}
|
||||
pub trait SclPin<T: Instance>: sealed::SclPin<T> + crate::gpio::Pin {}
|
||||
|
||||
macro_rules! impl_pin {
|
||||
($pin:ident, $instance:ident, $function:ident) => {
|
||||
impl sealed::$function<peripherals::$instance> for peripherals::$pin {}
|
||||
impl $function<peripherals::$instance> for peripherals::$pin {}
|
||||
};
|
||||
}
|
||||
|
||||
impl_pin!(PIN_0, I2C0, SdaPin);
|
||||
impl_pin!(PIN_1, I2C0, SclPin);
|
||||
impl_pin!(PIN_2, I2C1, SdaPin);
|
||||
impl_pin!(PIN_3, I2C1, SclPin);
|
||||
impl_pin!(PIN_4, I2C0, SdaPin);
|
||||
impl_pin!(PIN_5, I2C0, SclPin);
|
||||
impl_pin!(PIN_6, I2C1, SdaPin);
|
||||
impl_pin!(PIN_7, I2C1, SclPin);
|
||||
impl_pin!(PIN_8, I2C0, SdaPin);
|
||||
impl_pin!(PIN_9, I2C0, SclPin);
|
||||
impl_pin!(PIN_10, I2C1, SdaPin);
|
||||
impl_pin!(PIN_11, I2C1, SclPin);
|
||||
impl_pin!(PIN_12, I2C0, SdaPin);
|
||||
impl_pin!(PIN_13, I2C0, SclPin);
|
||||
impl_pin!(PIN_14, I2C1, SdaPin);
|
||||
impl_pin!(PIN_15, I2C1, SclPin);
|
||||
impl_pin!(PIN_16, I2C0, SdaPin);
|
||||
impl_pin!(PIN_17, I2C0, SclPin);
|
||||
impl_pin!(PIN_18, I2C1, SdaPin);
|
||||
impl_pin!(PIN_19, I2C1, SclPin);
|
||||
impl_pin!(PIN_20, I2C0, SdaPin);
|
||||
impl_pin!(PIN_21, I2C0, SclPin);
|
||||
impl_pin!(PIN_22, I2C1, SdaPin);
|
||||
impl_pin!(PIN_23, I2C1, SclPin);
|
||||
impl_pin!(PIN_24, I2C0, SdaPin);
|
||||
impl_pin!(PIN_25, I2C0, SclPin);
|
||||
impl_pin!(PIN_26, I2C1, SdaPin);
|
||||
impl_pin!(PIN_27, I2C1, SclPin);
|
||||
impl_pin!(PIN_28, I2C0, SdaPin);
|
||||
impl_pin!(PIN_29, I2C0, SclPin);
|
||||
Loading…
Reference in New Issue
Block a user