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Merge pull request #2073 from embassy-rs/rcc-no-spaghetti

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nrf/pac: reeport s and ns peripherals always independently of the current mode.
This commit is contained in:
Dario Nieuwenhuis 2023-10-16 17:43:13 +00:00 committed by GitHub
commit 889d482d2d
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 297 additions and 268 deletions
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316
embassy-nrf/src/chips/nrf5340_app.rs
View File

@ -6,10 +6,13 @@ pub mod pac {
// To avoid cfg spam, we remove _ns or _s suffixes here. // To avoid cfg spam, we remove _ns or _s suffixes here.
pub use nrf5340_app_pac::NVIC_PRIO_BITS; pub use nrf5340_app_pac::NVIC_PRIO_BITS;
#[cfg(feature="rt")]
#[doc(no_inline)]
pub use nrf5340_app_pac::interrupt;
#[doc(no_inline)] #[doc(no_inline)]
pub use nrf5340_app_pac::{ pub use nrf5340_app_pac::{
interrupt,
Interrupt, Interrupt,
Peripherals, Peripherals,
@ -60,156 +63,167 @@ pub mod pac {
wdt0_ns as wdt0, wdt0_ns as wdt0,
}; };
#[cfg(feature = "nrf5340-app-ns")] /// Non-Secure mode (NS) peripherals
#[doc(no_inline)] pub mod ns {
pub use nrf5340_app_pac::{ #[cfg(feature = "nrf5340-app-ns")]
CLOCK_NS as CLOCK, #[doc(no_inline)]
COMP_NS as COMP, pub use nrf5340_app_pac::{
CTRLAP_NS as CTRLAP, CLOCK_NS as CLOCK,
DCNF_NS as DCNF, COMP_NS as COMP,
DPPIC_NS as DPPIC, CTRLAP_NS as CTRLAP,
EGU0_NS as EGU0, DCNF_NS as DCNF,
EGU1_NS as EGU1, DPPIC_NS as DPPIC,
EGU2_NS as EGU2, EGU0_NS as EGU0,
EGU3_NS as EGU3, EGU1_NS as EGU1,
EGU4_NS as EGU4, EGU2_NS as EGU2,
EGU5_NS as EGU5, EGU3_NS as EGU3,
FPU_NS as FPU, EGU4_NS as EGU4,
GPIOTE1_NS as GPIOTE1, EGU5_NS as EGU5,
I2S0_NS as I2S0, FPU_NS as FPU,
IPC_NS as IPC, GPIOTE1_NS as GPIOTE1,
KMU_NS as KMU, I2S0_NS as I2S0,
LPCOMP_NS as LPCOMP, IPC_NS as IPC,
MUTEX_NS as MUTEX, KMU_NS as KMU,
NFCT_NS as NFCT, LPCOMP_NS as LPCOMP,
NVMC_NS as NVMC, MUTEX_NS as MUTEX,
OSCILLATORS_NS as OSCILLATORS, NFCT_NS as NFCT,
P0_NS as P0, NVMC_NS as NVMC,
P1_NS as P1, OSCILLATORS_NS as OSCILLATORS,
PDM0_NS as PDM0, P0_NS as P0,
POWER_NS as POWER, P1_NS as P1,
PWM0_NS as PWM0, PDM0_NS as PDM0,
PWM1_NS as PWM1, POWER_NS as POWER,
PWM2_NS as PWM2, PWM0_NS as PWM0,
PWM3_NS as PWM3, PWM1_NS as PWM1,
QDEC0_NS as QDEC0, PWM2_NS as PWM2,
QDEC1_NS as QDEC1, PWM3_NS as PWM3,
QSPI_NS as QSPI, QDEC0_NS as QDEC0,
REGULATORS_NS as REGULATORS, QDEC1_NS as QDEC1,
RESET_NS as RESET, QSPI_NS as QSPI,
RTC0_NS as RTC0, REGULATORS_NS as REGULATORS,
RTC1_NS as RTC1, RESET_NS as RESET,
SAADC_NS as SAADC, RTC0_NS as RTC0,
SPIM0_NS as SPIM0, RTC1_NS as RTC1,
SPIM1_NS as SPIM1, SAADC_NS as SAADC,
SPIM2_NS as SPIM2, SPIM0_NS as SPIM0,
SPIM3_NS as SPIM3, SPIM1_NS as SPIM1,
SPIM4_NS as SPIM4, SPIM2_NS as SPIM2,
SPIS0_NS as SPIS0, SPIM3_NS as SPIM3,
SPIS1_NS as SPIS1, SPIM4_NS as SPIM4,
SPIS2_NS as SPIS2, SPIS0_NS as SPIS0,
SPIS3_NS as SPIS3, SPIS1_NS as SPIS1,
TIMER0_NS as TIMER0, SPIS2_NS as SPIS2,
TIMER1_NS as TIMER1, SPIS3_NS as SPIS3,
TIMER2_NS as TIMER2, TIMER0_NS as TIMER0,
TWIM0_NS as TWIM0, TIMER1_NS as TIMER1,
TWIM1_NS as TWIM1, TIMER2_NS as TIMER2,
TWIM2_NS as TWIM2, TWIM0_NS as TWIM0,
TWIM3_NS as TWIM3, TWIM1_NS as TWIM1,
TWIS0_NS as TWIS0, TWIM2_NS as TWIM2,
TWIS1_NS as TWIS1, TWIM3_NS as TWIM3,
TWIS2_NS as TWIS2, TWIS0_NS as TWIS0,
TWIS3_NS as TWIS3, TWIS1_NS as TWIS1,
UARTE0_NS as UARTE0, TWIS2_NS as TWIS2,
UARTE1_NS as UARTE1, TWIS3_NS as TWIS3,
UARTE2_NS as UARTE2, UARTE0_NS as UARTE0,
UARTE3_NS as UARTE3, UARTE1_NS as UARTE1,
USBD_NS as USBD, UARTE2_NS as UARTE2,
USBREGULATOR_NS as USBREGULATOR, UARTE3_NS as UARTE3,
VMC_NS as VMC, USBD_NS as USBD,
WDT0_NS as WDT0, USBREGULATOR_NS as USBREGULATOR,
WDT1_NS as WDT1, VMC_NS as VMC,
}; WDT0_NS as WDT0,
WDT1_NS as WDT1,
};
}
#[cfg(feature = "nrf5340-app-s")] /// Secure mode (S) peripherals
#[doc(no_inline)] pub mod s {
pub use nrf5340_app_pac::{ #[cfg(feature = "nrf5340-app-s")]
CACHEDATA_S as CACHEDATA, #[doc(no_inline)]
CACHEINFO_S as CACHEINFO, pub use nrf5340_app_pac::{
CACHE_S as CACHE, CACHEDATA_S as CACHEDATA,
CLOCK_S as CLOCK, CACHEINFO_S as CACHEINFO,
COMP_S as COMP, CACHE_S as CACHE,
CRYPTOCELL_S as CRYPTOCELL, CLOCK_S as CLOCK,
CTI_S as CTI, COMP_S as COMP,
CTRLAP_S as CTRLAP, CRYPTOCELL_S as CRYPTOCELL,
DCNF_S as DCNF, CTI_S as CTI,
DPPIC_S as DPPIC, CTRLAP_S as CTRLAP,
EGU0_S as EGU0, DCNF_S as DCNF,
EGU1_S as EGU1, DPPIC_S as DPPIC,
EGU2_S as EGU2, EGU0_S as EGU0,
EGU3_S as EGU3, EGU1_S as EGU1,
EGU4_S as EGU4, EGU2_S as EGU2,
EGU5_S as EGU5, EGU3_S as EGU3,
FICR_S as FICR, EGU4_S as EGU4,
FPU_S as FPU, EGU5_S as EGU5,
GPIOTE0_S as GPIOTE0, FICR_S as FICR,
I2S0_S as I2S0, FPU_S as FPU,
IPC_S as IPC, GPIOTE0_S as GPIOTE0,
KMU_S as KMU, I2S0_S as I2S0,
LPCOMP_S as LPCOMP, IPC_S as IPC,
MUTEX_S as MUTEX, KMU_S as KMU,
NFCT_S as NFCT, LPCOMP_S as LPCOMP,
NVMC_S as NVMC, MUTEX_S as MUTEX,
OSCILLATORS_S as OSCILLATORS, NFCT_S as NFCT,
P0_S as P0, NVMC_S as NVMC,
P1_S as P1, OSCILLATORS_S as OSCILLATORS,
PDM0_S as PDM0, P0_S as P0,
POWER_S as POWER, P1_S as P1,
PWM0_S as PWM0, PDM0_S as PDM0,
PWM1_S as PWM1, POWER_S as POWER,
PWM2_S as PWM2, PWM0_S as PWM0,
PWM3_S as PWM3, PWM1_S as PWM1,
QDEC0_S as QDEC0, PWM2_S as PWM2,
QDEC1_S as QDEC1, PWM3_S as PWM3,
QSPI_S as QSPI, QDEC0_S as QDEC0,
REGULATORS_S as REGULATORS, QDEC1_S as QDEC1,
RESET_S as RESET, QSPI_S as QSPI,
RTC0_S as RTC0, REGULATORS_S as REGULATORS,
RTC1_S as RTC1, RESET_S as RESET,
SAADC_S as SAADC, RTC0_S as RTC0,
SPIM0_S as SPIM0, RTC1_S as RTC1,
SPIM1_S as SPIM1, SAADC_S as SAADC,
SPIM2_S as SPIM2, SPIM0_S as SPIM0,
SPIM3_S as SPIM3, SPIM1_S as SPIM1,
SPIM4_S as SPIM4, SPIM2_S as SPIM2,
SPIS0_S as SPIS0, SPIM3_S as SPIM3,
SPIS1_S as SPIS1, SPIM4_S as SPIM4,
SPIS2_S as SPIS2, SPIS0_S as SPIS0,
SPIS3_S as SPIS3, SPIS1_S as SPIS1,
SPU_S as SPU, SPIS2_S as SPIS2,
TAD_S as TAD, SPIS3_S as SPIS3,
TIMER0_S as TIMER0, SPU_S as SPU,
TIMER1_S as TIMER1, TAD_S as TAD,
TIMER2_S as TIMER2, TIMER0_S as TIMER0,
TWIM0_S as TWIM0, TIMER1_S as TIMER1,
TWIM1_S as TWIM1, TIMER2_S as TIMER2,
TWIM2_S as TWIM2, TWIM0_S as TWIM0,
TWIM3_S as TWIM3, TWIM1_S as TWIM1,
TWIS0_S as TWIS0, TWIM2_S as TWIM2,
TWIS1_S as TWIS1, TWIM3_S as TWIM3,
TWIS2_S as TWIS2, TWIS0_S as TWIS0,
TWIS3_S as TWIS3, TWIS1_S as TWIS1,
UARTE0_S as UARTE0, TWIS2_S as TWIS2,
UARTE1_S as UARTE1, TWIS3_S as TWIS3,
UARTE2_S as UARTE2, UARTE0_S as UARTE0,
UARTE3_S as UARTE3, UARTE1_S as UARTE1,
UICR_S as UICR, UARTE2_S as UARTE2,
USBD_S as USBD, UARTE3_S as UARTE3,
USBREGULATOR_S as USBREGULATOR, UICR_S as UICR,
VMC_S as VMC, USBD_S as USBD,
WDT0_S as WDT0, USBREGULATOR_S as USBREGULATOR,
WDT1_S as WDT1, VMC_S as VMC,
}; WDT0_S as WDT0,
WDT1_S as WDT1,
};
}
#[cfg(feature = "_ns")]
pub use ns::*;
#[cfg(feature = "_s")]
pub use s::*;
} }
/// The maximum buffer size that the EasyDMA can send/recv in one operation. /// The maximum buffer size that the EasyDMA can send/recv in one operation.

5
embassy-nrf/src/chips/nrf5340_net.rs
View File

@ -7,9 +7,12 @@ pub mod pac {
pub use nrf5340_net_pac::NVIC_PRIO_BITS; pub use nrf5340_net_pac::NVIC_PRIO_BITS;
#[cfg(feature="rt")]
#[doc(no_inline)]
pub use nrf5340_net_pac::interrupt;
#[doc(no_inline)] #[doc(no_inline)]
pub use nrf5340_net_pac::{ pub use nrf5340_net_pac::{
interrupt,
Interrupt, Interrupt,
Peripherals, Peripherals,

244
embassy-nrf/src/chips/nrf9160.rs
View File

@ -7,9 +7,12 @@ pub mod pac {
pub use nrf9160_pac::NVIC_PRIO_BITS; pub use nrf9160_pac::NVIC_PRIO_BITS;
#[cfg(feature="rt")]
#[doc(no_inline)]
pub use nrf9160_pac::interrupt;
#[doc(no_inline)] #[doc(no_inline)]
pub use nrf9160_pac::{ pub use nrf9160_pac::{
interrupt,
Interrupt, Interrupt,
cc_host_rgf_s as cc_host_rgf, cc_host_rgf_s as cc_host_rgf,
@ -45,122 +48,131 @@ pub mod pac {
wdt_ns as wdt, wdt_ns as wdt,
}; };
#[cfg(feature = "nrf9160-ns")] /// Non-Secure mode (NS) peripherals
#[doc(no_inline)] pub mod ns {
pub use nrf9160_pac::{ #[doc(no_inline)]
CLOCK_NS as CLOCK, pub use nrf9160_pac::{
DPPIC_NS as DPPIC, CLOCK_NS as CLOCK,
EGU0_NS as EGU0, DPPIC_NS as DPPIC,
EGU1_NS as EGU1, EGU0_NS as EGU0,
EGU2_NS as EGU2, EGU1_NS as EGU1,
EGU3_NS as EGU3, EGU2_NS as EGU2,
EGU4_NS as EGU4, EGU3_NS as EGU3,
EGU5_NS as EGU5, EGU4_NS as EGU4,
FPU_NS as FPU, EGU5_NS as EGU5,
GPIOTE1_NS as GPIOTE1, FPU_NS as FPU,
I2S_NS as I2S, GPIOTE1_NS as GPIOTE1,
IPC_NS as IPC, I2S_NS as I2S,
KMU_NS as KMU, IPC_NS as IPC,
NVMC_NS as NVMC, KMU_NS as KMU,
P0_NS as P0, NVMC_NS as NVMC,
PDM_NS as PDM, P0_NS as P0,
POWER_NS as POWER, PDM_NS as PDM,
PWM0_NS as PWM0, POWER_NS as POWER,
PWM1_NS as PWM1, PWM0_NS as PWM0,
PWM2_NS as PWM2, PWM1_NS as PWM1,
PWM3_NS as PWM3, PWM2_NS as PWM2,
REGULATORS_NS as REGULATORS, PWM3_NS as PWM3,
RTC0_NS as RTC0, REGULATORS_NS as REGULATORS,
RTC1_NS as RTC1, RTC0_NS as RTC0,
SAADC_NS as SAADC, RTC1_NS as RTC1,
SPIM0_NS as SPIM0, SAADC_NS as SAADC,
SPIM1_NS as SPIM1, SPIM0_NS as SPIM0,
SPIM2_NS as SPIM2, SPIM1_NS as SPIM1,
SPIM3_NS as SPIM3, SPIM2_NS as SPIM2,
SPIS0_NS as SPIS0, SPIM3_NS as SPIM3,
SPIS1_NS as SPIS1, SPIS0_NS as SPIS0,
SPIS2_NS as SPIS2, SPIS1_NS as SPIS1,
SPIS3_NS as SPIS3, SPIS2_NS as SPIS2,
TIMER0_NS as TIMER0, SPIS3_NS as SPIS3,
TIMER1_NS as TIMER1, TIMER0_NS as TIMER0,
TIMER2_NS as TIMER2, TIMER1_NS as TIMER1,
TWIM0_NS as TWIM0, TIMER2_NS as TIMER2,
TWIM1_NS as TWIM1, TWIM0_NS as TWIM0,
TWIM2_NS as TWIM2, TWIM1_NS as TWIM1,
TWIM3_NS as TWIM3, TWIM2_NS as TWIM2,
TWIS0_NS as TWIS0, TWIM3_NS as TWIM3,
TWIS1_NS as TWIS1, TWIS0_NS as TWIS0,
TWIS2_NS as TWIS2, TWIS1_NS as TWIS1,
TWIS3_NS as TWIS3, TWIS2_NS as TWIS2,
UARTE0_NS as UARTE0, TWIS3_NS as TWIS3,
UARTE1_NS as UARTE1, UARTE0_NS as UARTE0,
UARTE2_NS as UARTE2, UARTE1_NS as UARTE1,
UARTE3_NS as UARTE3, UARTE2_NS as UARTE2,
VMC_NS as VMC, UARTE3_NS as UARTE3,
WDT_NS as WDT, VMC_NS as VMC,
}; WDT_NS as WDT,
};
}
#[cfg(feature = "nrf9160-s")] /// Secure mode (S) peripherals
#[doc(no_inline)] pub mod s {
pub use nrf9160_pac::{ #[doc(no_inline)]
CC_HOST_RGF_S as CC_HOST_RGF, pub use nrf9160_pac::{
CLOCK_S as CLOCK, CC_HOST_RGF_S as CC_HOST_RGF,
CRYPTOCELL_S as CRYPTOCELL, CLOCK_S as CLOCK,
CTRL_AP_PERI_S as CTRL_AP_PERI, CRYPTOCELL_S as CRYPTOCELL,
DPPIC_S as DPPIC, CTRL_AP_PERI_S as CTRL_AP_PERI,
EGU0_S as EGU0, DPPIC_S as DPPIC,
EGU1_S as EGU1, EGU0_S as EGU0,
EGU2_S as EGU2, EGU1_S as EGU1,
EGU3_S as EGU3, EGU2_S as EGU2,
EGU4_S as EGU4, EGU3_S as EGU3,
EGU5_S as EGU5, EGU4_S as EGU4,
FICR_S as FICR, EGU5_S as EGU5,
FPU_S as FPU, FICR_S as FICR,
GPIOTE0_S as GPIOTE0, FPU_S as FPU,
I2S_S as I2S, GPIOTE0_S as GPIOTE0,
IPC_S as IPC, I2S_S as I2S,
KMU_S as KMU, IPC_S as IPC,
NVMC_S as NVMC, KMU_S as KMU,
P0_S as P0, NVMC_S as NVMC,
PDM_S as PDM, P0_S as P0,
POWER_S as POWER, PDM_S as PDM,
PWM0_S as PWM0, POWER_S as POWER,
PWM1_S as PWM1, PWM0_S as PWM0,
PWM2_S as PWM2, PWM1_S as PWM1,
PWM3_S as PWM3, PWM2_S as PWM2,
REGULATORS_S as REGULATORS, PWM3_S as PWM3,
RTC0_S as RTC0, REGULATORS_S as REGULATORS,
RTC1_S as RTC1, RTC0_S as RTC0,
SAADC_S as SAADC, RTC1_S as RTC1,
SPIM0_S as SPIM0, SAADC_S as SAADC,
SPIM1_S as SPIM1, SPIM0_S as SPIM0,
SPIM2_S as SPIM2, SPIM1_S as SPIM1,
SPIM3_S as SPIM3, SPIM2_S as SPIM2,
SPIS0_S as SPIS0, SPIM3_S as SPIM3,
SPIS1_S as SPIS1, SPIS0_S as SPIS0,
SPIS2_S as SPIS2, SPIS1_S as SPIS1,
SPIS3_S as SPIS3, SPIS2_S as SPIS2,
SPU_S as SPU, SPIS3_S as SPIS3,
TAD_S as TAD, SPU_S as SPU,
TIMER0_S as TIMER0, TAD_S as TAD,
TIMER1_S as TIMER1, TIMER0_S as TIMER0,
TIMER2_S as TIMER2, TIMER1_S as TIMER1,
TWIM0_S as TWIM0, TIMER2_S as TIMER2,
TWIM1_S as TWIM1, TWIM0_S as TWIM0,
TWIM2_S as TWIM2, TWIM1_S as TWIM1,
TWIM3_S as TWIM3, TWIM2_S as TWIM2,
TWIS0_S as TWIS0, TWIM3_S as TWIM3,
TWIS1_S as TWIS1, TWIS0_S as TWIS0,
TWIS2_S as TWIS2, TWIS1_S as TWIS1,
TWIS3_S as TWIS3, TWIS2_S as TWIS2,
UARTE0_S as UARTE0, TWIS3_S as TWIS3,
UARTE1_S as UARTE1, UARTE0_S as UARTE0,
UARTE2_S as UARTE2, UARTE1_S as UARTE1,
UARTE3_S as UARTE3, UARTE2_S as UARTE2,
UICR_S as UICR, UARTE3_S as UARTE3,
VMC_S as VMC, UICR_S as UICR,
WDT_S as WDT, VMC_S as VMC,
}; WDT_S as WDT,
};
}
#[cfg(feature = "_ns")]
pub use ns::*;
#[cfg(feature = "_s")]
pub use s::*;
} }
/// The maximum buffer size that the EasyDMA can send/recv in one operation. /// The maximum buffer size that the EasyDMA can send/recv in one operation.