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feat: new_txonly_nosck in spim

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This commit is contained in:
swanandx 2024-01-03 19:25:09 +05:30
parent face031245
commit 8352d13cfd
1 changed files with 18 additions and 5 deletions
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21
embassy-nrf/src/spim.rs
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@ -99,7 +99,7 @@ impl<'d, T: Instance> Spim<'d, T> {
into_ref!(sck, miso, mosi); into_ref!(sck, miso, mosi);
Self::new_inner( Self::new_inner(
spim, spim,
sck.map_into(), Some(sck.map_into()),
Some(miso.map_into()), Some(miso.map_into()),
Some(mosi.map_into()), Some(mosi.map_into()),
config, config,
@ -115,7 +115,7 @@ impl<'d, T: Instance> Spim<'d, T> {
config: Config, config: Config,
) -> Self { ) -> Self {
into_ref!(sck, mosi); into_ref!(sck, mosi);
Self::new_inner(spim, sck.map_into(), None, Some(mosi.map_into()), config) Self::new_inner(spim, Some(sck.map_into()), None, Some(mosi.map_into()), config)
} }
/// Create a new SPIM driver, capable of RX only (MISO only). /// Create a new SPIM driver, capable of RX only (MISO only).
@ -127,12 +127,23 @@ impl<'d, T: Instance> Spim<'d, T> {
config: Config, config: Config,
) -> Self { ) -> Self {
into_ref!(sck, miso); into_ref!(sck, miso);
Self::new_inner(spim, sck.map_into(), Some(miso.map_into()), None, config) Self::new_inner(spim, Some(sck.map_into()), Some(miso.map_into()), None, config)
}
/// Create a new SPIM driver, capable of TX only (MOSI only), without SCK pin.
pub fn new_txonly_nosck(
spim: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
mosi: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Self {
into_ref!(mosi);
Self::new_inner(spim, None, None, Some(mosi.map_into()), config)
} }
fn new_inner( fn new_inner(
spim: impl Peripheral<P = T> + 'd, spim: impl Peripheral<P = T> + 'd,
sck: PeripheralRef<'d, AnyPin>, sck: Option<PeripheralRef<'d, AnyPin>>,
miso: Option<PeripheralRef<'d, AnyPin>>, miso: Option<PeripheralRef<'d, AnyPin>>,
mosi: Option<PeripheralRef<'d, AnyPin>>, mosi: Option<PeripheralRef<'d, AnyPin>>,
config: Config, config: Config,
@ -142,7 +153,9 @@ impl<'d, T: Instance> Spim<'d, T> {
let r = T::regs(); let r = T::regs();
// Configure pins // Configure pins
if let Some(sck) = &sck {
sck.conf().write(|w| w.dir().output().drive().h0h1()); sck.conf().write(|w| w.dir().output().drive().h0h1());
}
if let Some(mosi) = &mosi { if let Some(mosi) = &mosi {
mosi.conf().write(|w| w.dir().output().drive().h0h1()); mosi.conf().write(|w| w.dir().output().drive().h0h1());
} }