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feat: new_txonly_nosck in spim
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parent
face031245
commit
8352d13cfd
@ -99,7 +99,7 @@ impl<'d, T: Instance> Spim<'d, T> {
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into_ref!(sck, miso, mosi);
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Self::new_inner(
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spim,
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sck.map_into(),
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Some(sck.map_into()),
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Some(miso.map_into()),
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Some(mosi.map_into()),
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config,
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@ -115,7 +115,7 @@ impl<'d, T: Instance> Spim<'d, T> {
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config: Config,
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) -> Self {
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into_ref!(sck, mosi);
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Self::new_inner(spim, sck.map_into(), None, Some(mosi.map_into()), config)
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Self::new_inner(spim, Some(sck.map_into()), None, Some(mosi.map_into()), config)
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}
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/// Create a new SPIM driver, capable of RX only (MISO only).
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@ -127,12 +127,23 @@ impl<'d, T: Instance> Spim<'d, T> {
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config: Config,
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) -> Self {
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into_ref!(sck, miso);
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Self::new_inner(spim, sck.map_into(), Some(miso.map_into()), None, config)
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Self::new_inner(spim, Some(sck.map_into()), Some(miso.map_into()), None, config)
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}
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/// Create a new SPIM driver, capable of TX only (MOSI only), without SCK pin.
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pub fn new_txonly_nosck(
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spim: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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mosi: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(mosi);
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Self::new_inner(spim, None, None, Some(mosi.map_into()), config)
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}
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fn new_inner(
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spim: impl Peripheral<P = T> + 'd,
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sck: PeripheralRef<'d, AnyPin>,
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sck: Option<PeripheralRef<'d, AnyPin>>,
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miso: Option<PeripheralRef<'d, AnyPin>>,
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mosi: Option<PeripheralRef<'d, AnyPin>>,
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config: Config,
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@ -142,7 +153,9 @@ impl<'d, T: Instance> Spim<'d, T> {
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let r = T::regs();
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// Configure pins
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sck.conf().write(|w| w.dir().output().drive().h0h1());
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if let Some(sck) = &sck {
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sck.conf().write(|w| w.dir().output().drive().h0h1());
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}
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if let Some(mosi) = &mosi {
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mosi.conf().write(|w| w.dir().output().drive().h0h1());
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}
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