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revise i2c trait
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xoviat
parent
a3a36517bd
commit
7a46e66298
@ -97,6 +97,7 @@ pub trait Read<A: AddressMode = SevenBitAddress> {
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type Error;
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type ReadFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a;
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type WriteFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a;
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/// Reads enough bytes from slave with `address` to fill `buffer`
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///
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@ -117,14 +118,6 @@ pub trait Read<A: AddressMode = SevenBitAddress> {
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/// - `NMAK` = master no acknowledge
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/// - `SP` = stop condition
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fn read<'a>(self: Pin<&'a mut Self>, address: A, buffer: &mut [u8]) -> Self::ReadFuture<'a>;
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}
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/// Blocking write
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pub trait Write<A: AddressMode = SevenBitAddress> {
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/// Error type
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type Error;
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type WriteFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a;
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/// Sends bytes to slave with address `address`
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///
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@ -144,242 +137,3 @@ pub trait Write<A: AddressMode = SevenBitAddress> {
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/// - `SP` = stop condition
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fn write<'a>(self: Pin<&'a mut Self>, address: A, bytes: &[u8]) -> Self::WriteFuture<'a>;
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}
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/// Blocking write (iterator version)
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pub trait WriteIter<A: AddressMode = SevenBitAddress> {
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/// Error type
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type Error;
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type WriteIterFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a;
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/// Sends bytes to slave with address `address`
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///
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/// # I2C Events (contract)
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///
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/// Same as `Write`
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fn write_iter<'a, B>(
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self: Pin<&'a mut Self>,
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address: A,
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bytes: B,
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) -> Self::WriteIterFuture<'a>
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where
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B: IntoIterator<Item = u8>;
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}
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/// Blocking write + read
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pub trait WriteRead<A: AddressMode = SevenBitAddress> {
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/// Error type
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type Error;
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type WriteReadFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a;
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/// Sends bytes to slave with address `address` and then reads enough bytes to fill `buffer` *in a
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/// single transaction*
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///
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/// # I2C Events (contract)
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///
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/// ``` text
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/// Master: ST SAD+W O0 O1 ... OM SR SAD+R MAK MAK ... NMAK SP
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/// Slave: SAK SAK SAK ... SAK SAK I0 I1 ... IN
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/// ```
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///
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/// Where
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///
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/// - `ST` = start condition
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/// - `SAD+W` = slave address followed by bit 0 to indicate writing
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/// - `SAK` = slave acknowledge
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/// - `Oi` = ith outgoing byte of data
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/// - `SR` = repeated start condition
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/// - `SAD+R` = slave address followed by bit 1 to indicate reading
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/// - `Ii` = ith incoming byte of data
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/// - `MAK` = master acknowledge
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/// - `NMAK` = master no acknowledge
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/// - `SP` = stop condition
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fn write_read<'a>(
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self: Pin<&'a mut Self>,
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address: A,
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bytes: &[u8],
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buffer: &mut [u8],
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) -> Self::WriteReadFuture<'a>;
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}
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/// Blocking write (iterator version) + read
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pub trait WriteIterRead<A: AddressMode = SevenBitAddress> {
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/// Error type
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type Error;
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type WriteIterReadFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a;
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/// Sends bytes to slave with address `address` and then reads enough bytes to fill `buffer` *in a
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/// single transaction*
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///
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/// # I2C Events (contract)
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///
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/// Same as the `WriteRead` trait
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fn write_iter_read<'a, B>(
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self: Pin<&'a mut Self>,
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address: A,
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bytes: B,
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buffer: &mut [u8],
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) -> Self::WriteIterReadFuture<'a>
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where
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B: IntoIterator<Item = u8>;
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}
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/// Transactional I2C operation.
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///
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/// Several operations can be combined as part of a transaction.
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#[derive(Debug, PartialEq)]
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pub enum Operation<'a> {
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/// Read data into the provided buffer
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Read(&'a mut [u8]),
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/// Write data from the provided buffer
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Write(&'a [u8]),
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}
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/// Transactional I2C interface.
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///
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/// This allows combining operations within an I2C transaction.
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pub trait Transactional<A: AddressMode = SevenBitAddress> {
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/// Error type
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type Error;
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type TransactionalFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a;
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/// Execute the provided operations on the I2C bus.
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///
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/// Transaction contract:
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/// - Before executing the first operation an ST is sent automatically. This is followed by SAD+R/W as appropriate.
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/// - Data from adjacent operations of the same type are sent after each other without an SP or SR.
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/// - Between adjacent operations of a different type an SR and SAD+R/W is sent.
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/// - After executing the last operation an SP is sent automatically.
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/// - If the last operation is a `Read` the master does not send an acknowledge for the last byte.
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///
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/// - `ST` = start condition
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/// - `SAD+R/W` = slave address followed by bit 1 to indicate reading or 0 to indicate writing
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/// - `SR` = repeated start condition
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/// - `SP` = stop condition
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fn exec<'a>(
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&mut self,
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address: A,
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operations: &mut [Operation<'a>],
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) -> Self::TransactionalFuture<'a>;
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}
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/// Transactional I2C interface (iterator version).
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///
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/// This allows combining operation within an I2C transaction.
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pub trait TransactionalIter<A: AddressMode = SevenBitAddress> {
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/// Error type
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type Error;
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type TransactionalIterFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a;
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/// Execute the provided operations on the I2C bus (iterator version).
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///
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/// Transaction contract:
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/// - Before executing the first operation an ST is sent automatically. This is followed by SAD+R/W as appropriate.
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/// - Data from adjacent operations of the same type are sent after each other without an SP or SR.
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/// - Between adjacent operations of a different type an SR and SAD+R/W is sent.
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/// - After executing the last operation an SP is sent automatically.
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/// - If the last operation is a `Read` the master does not send an acknowledge for the last byte.
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///
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/// - `ST` = start condition
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/// - `SAD+R/W` = slave address followed by bit 1 to indicate reading or 0 to indicate writing
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/// - `SR` = repeated start condition
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/// - `SP` = stop condition
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fn exec_iter<'a, O>(&mut self, address: A, operations: O) -> Self::TransactionalIterFuture<'a>
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where
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O: IntoIterator<Item = Operation<'a>>;
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}
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/// Default implementation of `blocking::i2c::Write`, `blocking::i2c::Read` and
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/// `blocking::i2c::WriteRead` traits for `blocking::i2c::Transactional` implementers.
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///
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/// If you implement `blocking::i2c::Transactional` for your I2C peripheral,
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/// you can use this default implementation so that you do not need to implement
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/// the `blocking::i2c::Write`, `blocking::i2c::Read` and `blocking::i2c::WriteRead`
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/// traits as well.
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/// ```
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/// use embedded_hal::blocking::i2c;
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///
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/// struct I2c1;
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///
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/// impl i2c::Transactional<i2c::SevenBitAddress> for I2c1 {
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/// # type Error = ();
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/// fn try_exec<'a>(
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/// &mut self,
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/// address: i2c::SevenBitAddress,
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/// operations: &mut [i2c::Operation<'a>],
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/// ) -> Result<(), Self::Error> {
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/// // ...
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/// # Ok(())
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/// }
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/// }
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///
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/// // This is all you need to do:
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/// impl i2c::transactional::Default<i2c::SevenBitAddress> for I2c1 {};
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///
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/// // Then you can use `Write` and so on:
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/// use i2c::Write;
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///
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/// let mut i2c1 = I2c1{};
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/// i2c1.try_write(0x01, &[0xAB, 0xCD]).unwrap();
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/// ```
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pub mod transactional {
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use core::future::Future;
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use super::{AddressMode, Operation, Read, Transactional, Write, WriteRead};
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/// Default implementation of `blocking::i2c::Write`, `blocking::i2c::Read` and
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/// `blocking::i2c::WriteRead` traits for `blocking::i2c::Transactional` implementers.
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pub trait Default<A: AddressMode>: Transactional<A> {}
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// impl<A, E, S> Write<A> for S
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// where
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// A: AddressMode + 'static,
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// S: self::Default<A> + Transactional<A, Error = E> + 'static,
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// E: 'static,
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// {
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// type Error = E;
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//
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// type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a;
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//
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// fn write<'a>(&mut self, address: A, bytes: &[u8]) -> Self::WriteFuture<'a> {
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// self.exec(address, &mut [Operation::Write(bytes)])
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// }
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// }
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/*
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impl<A, E, S> Read<A> for S
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where
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A: AddressMode,
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S: self::Default<A> + Transactional<A, Error = E>,
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{
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type Error = E;
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fn read(&mut self, address: A, buffer: &mut [u8]) -> Result<(), Self::Error> {
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self.exec(address, &mut [Operation::Read(buffer)])
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}
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}
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impl<A, E, S> WriteRead<A> for S
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where
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A: AddressMode,
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S: self::Default<A> + Transactional<A, Error = E>,
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{
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type Error = E;
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fn write_read(
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&mut self,
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address: A,
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bytes: &[u8],
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buffer: &mut [u8],
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) -> Result<(), Self::Error> {
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self.exec(
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address,
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&mut [Operation::Write(bytes), Operation::Read(buffer)],
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)
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}
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}
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*/
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}
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