From 555231aeb510ed17996c2446ad412aefd4258cb3 Mon Sep 17 00:00:00 2001
From: elagil <elagil@takanome.de>
Date: Wed, 6 Nov 2024 19:46:52 +0100
Subject: [PATCH 1/2] chore: update stm32 data source

---
 embassy-stm32/Cargo.toml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 6ab6e162e..e2ba4fd60 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -72,7 +72,7 @@ rand_core = "0.6.3"
 sdio-host = "0.5.0"
 critical-section = "1.1"
 #stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9b7414490b10ffbd5beb1b0dcf14adb018cbe37f" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7bb5f235587c3a6886a7be1c8f58fdf22c5257f3" }
 
 vcell = "0.1.3"
 nb = "1.0.0"
@@ -101,7 +101,7 @@ proc-macro2 = "1.0.36"
 quote = "1.0.15"
 
 #stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9b7414490b10ffbd5beb1b0dcf14adb018cbe37f", default-features = false, features = ["metadata"] }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7bb5f235587c3a6886a7be1c8f58fdf22c5257f3", default-features = false, features = ["metadata"] }
 
 [features]
 default = ["rt"]

From e69be0a23bc182a78f2647cc1a739910a1a8e985 Mon Sep 17 00:00:00 2001
From: elagil <elagil@takanome.de>
Date: Wed, 6 Nov 2024 19:46:55 +0100
Subject: [PATCH 2/2] fix: STM32U5 RCC fields

---
 embassy-stm32/src/rcc/u5.rs | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 28545ca51..1e2bfe62d 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -279,8 +279,10 @@ pub(crate) unsafe fn init(config: Config) {
         hsi48: hsi48,
         rtc: rtc,
         hse: hse,
+        hse_div_2: hse.map(|clk| clk / 2u32),
         hsi: hsi,
         pll1_p: pll1.p,
+        pll1_p_div_2: pll1.p.map(|clk| clk / 2u32),
         pll1_q: pll1.q,
         pll1_r: pll1.r,
         pll2_p: pll2.p,