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feat(pwm): allow specifying OutputDrive for PWM channels

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This commit is contained in:
Giona Imperatori 2024-07-01 17:20:42 +02:00
parent bd0243d12f
commit 7884babb9d
2 changed files with 54 additions and 5 deletions
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1
embassy-nrf/CHANGELOG.md
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@ -24,6 +24,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- spi: Add support for configuring bit order for bus
- pwm: Expose `pwm::PWM_CLK_HZ` and add `is_enabled` method
- gpio: Drop GPIO Pin generics (API break)
- pwm: Allow specifying OutputDrive for PWM channels
## 0.1.0 - 2024-01-12

58
embassy-nrf/src/pwm.rs
View File

@ -6,7 +6,7 @@ use core::sync::atomic::{compiler_fence, Ordering};
use embassy_hal_internal::{into_ref, PeripheralRef};
use crate::gpio::{AnyPin, Pin as GpioPin, PselBits, SealedPin as _};
use crate::gpio::{convert_drive, AnyPin, OutputDrive, Pin as GpioPin, PselBits, SealedPin as _};
use crate::ppi::{Event, Task};
use crate::util::slice_in_ram_or;
use crate::{interrupt, pac, Peripheral};
@ -128,19 +128,23 @@ impl<'d, T: Instance> SequencePwm<'d, T> {
if let Some(pin) = &ch0 {
pin.set_low();
pin.conf().write(|w| w.dir().output());
pin.conf()
.write(|w| w.dir().output().drive().variant(convert_drive(config.ch0_drive)));
}
if let Some(pin) = &ch1 {
pin.set_low();
pin.conf().write(|w| w.dir().output());
pin.conf()
.write(|w| w.dir().output().drive().variant(convert_drive(config.ch1_drive)));
}
if let Some(pin) = &ch2 {
pin.set_low();
pin.conf().write(|w| w.dir().output());
pin.conf()
.write(|w| w.dir().output().drive().variant(convert_drive(config.ch2_drive)));
}
if let Some(pin) = &ch3 {
pin.set_low();
pin.conf().write(|w| w.dir().output());
pin.conf()
.write(|w| w.dir().output().drive().variant(convert_drive(config.ch3_drive)));
}
r.psel.out[0].write(|w| unsafe { w.bits(ch0.psel_bits()) });
@ -319,6 +323,14 @@ pub struct Config {
pub prescaler: Prescaler,
/// How a sequence is read from RAM and is spread to the compare register
pub sequence_load: SequenceLoad,
/// Drive strength for the channel 0 line.
pub ch0_drive: OutputDrive,
/// Drive strength for the channel 1 line.
pub ch1_drive: OutputDrive,
/// Drive strength for the channel 2 line.
pub ch2_drive: OutputDrive,
/// Drive strength for the channel 3 line.
pub ch3_drive: OutputDrive,
}
impl Default for Config {
@ -328,6 +340,10 @@ impl Default for Config {
max_duty: 1000,
prescaler: Prescaler::Div16,
sequence_load: SequenceLoad::Common,
ch0_drive: OutputDrive::Standard,
ch1_drive: OutputDrive::Standard,
ch2_drive: OutputDrive::Standard,
ch3_drive: OutputDrive::Standard,
}
}
}
@ -815,6 +831,38 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
let max_duty = self.max_duty() as u32;
clk / max_duty
}
/// Sets the PWM-Channel0 output drive strength
#[inline(always)]
pub fn set_ch0_drive(&self, drive: OutputDrive) {
if let Some(pin) = &self.ch0 {
pin.conf().write(|w| w.drive().variant(convert_drive(drive)));
}
}
/// Sets the PWM-Channel1 output drive strength
#[inline(always)]
pub fn set_ch1_drive(&self, drive: OutputDrive) {
if let Some(pin) = &self.ch1 {
pin.conf().write(|w| w.drive().variant(convert_drive(drive)));
}
}
/// Sets the PWM-Channel2 output drive strength
#[inline(always)]
pub fn set_ch2_drive(&self, drive: OutputDrive) {
if let Some(pin) = &self.ch2 {
pin.conf().write(|w| w.drive().variant(convert_drive(drive)));
}
}
/// Sets the PWM-Channel3 output drive strength
#[inline(always)]
pub fn set_ch3_drive(&self, drive: OutputDrive) {
if let Some(pin) = &self.ch3 {
pin.conf().write(|w| w.drive().variant(convert_drive(drive)));
}
}
}
impl<'a, T: Instance> Drop for SimplePwm<'a, T> {