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Add critical sections to avoid USB OTG Errata
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e38f1011d6
commit
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@ -672,6 +672,10 @@ impl<'d, T: Instance> Bus<'d, T> {
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let r = T::regs();
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// ERRATA NOTE: Don't interrupt FIFOs being written to. The interrupt
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// handler COULD interrupt us here and do FIFO operations, so ensure
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// the interrupt does not occur.
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critical_section::with(|_| {
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// Configure RX fifo size. All endpoints share the same FIFO area.
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let rx_fifo_size_words = RX_FIFO_EXTRA_SIZE_WORDS + ep_fifo_size(&self.ep_out);
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trace!("configuring rx fifo size={}", rx_fifo_size_words);
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@ -711,6 +715,8 @@ impl<'d, T: Instance> Bus<'d, T> {
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w.set_txfflsh(true);
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w.set_txfnum(0x10);
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});
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});
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loop {
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let x = r.grstctl().read();
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if !x.rxfflsh() && !x.txfflsh() {
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@ -1208,6 +1214,11 @@ impl<'d, T: Instance> embassy_usb_driver::EndpointIn for Endpoint<'d, T, In> {
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.await
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}
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// ERRATA: Transmit data FIFO is corrupted when a write sequence to the FIFO is interrupted with
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// accesses to certain OTG_FS registers.
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//
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// Prevent the interrupt (which might poke FIFOs) from executing while copying data to FIFOs.
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critical_section::with(|_| {
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// Setup transfer size
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r.dieptsiz(index).write(|w| {
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w.set_mcnt(1);
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@ -1229,6 +1240,7 @@ impl<'d, T: Instance> embassy_usb_driver::EndpointIn for Endpoint<'d, T, In> {
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tmp[0..chunk.len()].copy_from_slice(chunk);
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r.fifo(index).write_value(regs::Fifo(u32::from_ne_bytes(tmp)));
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}
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});
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trace!("write done ep={:?}", self.info.addr);
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