Add critical sections to avoid USB OTG Errata

This commit is contained in:
James Munns 2024-04-16 12:07:40 +02:00
parent e38f1011d6
commit 75352d181c

View File

@ -672,6 +672,10 @@ impl<'d, T: Instance> Bus<'d, T> {
let r = T::regs();
// ERRATA NOTE: Don't interrupt FIFOs being written to. The interrupt
// handler COULD interrupt us here and do FIFO operations, so ensure
// the interrupt does not occur.
critical_section::with(|_| {
// Configure RX fifo size. All endpoints share the same FIFO area.
let rx_fifo_size_words = RX_FIFO_EXTRA_SIZE_WORDS + ep_fifo_size(&self.ep_out);
trace!("configuring rx fifo size={}", rx_fifo_size_words);
@ -711,6 +715,8 @@ impl<'d, T: Instance> Bus<'d, T> {
w.set_txfflsh(true);
w.set_txfnum(0x10);
});
});
loop {
let x = r.grstctl().read();
if !x.rxfflsh() && !x.txfflsh() {
@ -1208,6 +1214,11 @@ impl<'d, T: Instance> embassy_usb_driver::EndpointIn for Endpoint<'d, T, In> {
.await
}
// ERRATA: Transmit data FIFO is corrupted when a write sequence to the FIFO is interrupted with
// accesses to certain OTG_FS registers.
//
// Prevent the interrupt (which might poke FIFOs) from executing while copying data to FIFOs.
critical_section::with(|_| {
// Setup transfer size
r.dieptsiz(index).write(|w| {
w.set_mcnt(1);
@ -1229,6 +1240,7 @@ impl<'d, T: Instance> embassy_usb_driver::EndpointIn for Endpoint<'d, T, In> {
tmp[0..chunk.len()].copy_from_slice(chunk);
r.fifo(index).write_value(regs::Fifo(u32::from_ne_bytes(tmp)));
}
});
trace!("write done ep={:?}", self.info.addr);