From 7231032f977fe4a1a486dfd963f7105b01bf684d Mon Sep 17 00:00:00 2001
From: Christian Enderle <mail@chrenderle.de>
Date: Thu, 7 Nov 2024 13:23:39 +0100
Subject: [PATCH] RCC: added msik for stm32u5

---
 embassy-stm32/src/rcc/u5.rs | 42 +++++++++++++++++++++++++++++++------
 1 file changed, 36 insertions(+), 6 deletions(-)

diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 1e2bfe62d..bb3d5f320 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -62,7 +62,8 @@ pub struct Pll {
 #[derive(Clone, Copy)]
 pub struct Config {
     // base clock sources
-    pub msi: Option<MSIRange>,
+    pub msis: Option<MSIRange>,
+    pub msik: Option<MSIRange>,
     pub hsi: bool,
     pub hse: Option<Hse>,
     pub hsi48: Option<super::Hsi48Config>,
@@ -94,7 +95,8 @@ pub struct Config {
 impl Default for Config {
     fn default() -> Self {
         Self {
-            msi: Some(Msirange::RANGE_4MHZ),
+            msis: Some(Msirange::RANGE_4MHZ),
+            msik: Some(Msirange::RANGE_4MHZ),
             hse: None,
             hsi: false,
             hsi48: Some(Default::default()),
@@ -118,7 +120,7 @@ pub(crate) unsafe fn init(config: Config) {
     PWR.vosr().modify(|w| w.set_vos(config.voltage_range));
     while !PWR.vosr().read().vosrdy() {}
 
-    let msi = config.msi.map(|range| {
+    let msis = config.msis.map(|range| {
         // Check MSI output per RM0456 § 11.4.10
         match config.voltage_range {
             VoltageScale::RANGE4 => {
@@ -147,6 +149,34 @@ pub(crate) unsafe fn init(config: Config) {
         msirange_to_hertz(range)
     });
 
+    let msik = config.msik.map(|range| {
+        // Check MSI output per RM0456 § 11.4.10
+        match config.voltage_range {
+            VoltageScale::RANGE4 => {
+                assert!(msirange_to_hertz(range).0 <= 24_000_000);
+            }
+            _ => {}
+        }
+
+        // RM0456 § 11.8.2: spin until MSIS is off or MSIS is ready before setting its range
+        loop {
+            let cr = RCC.cr().read();
+            if cr.msikon() == false || cr.msikrdy() == true {
+                break;
+            }
+        }
+
+        RCC.icscr1().modify(|w| {
+            w.set_msikrange(range);
+            w.set_msirgsel(Msirgsel::ICSCR1);
+        });
+        RCC.cr().write(|w| {
+            w.set_msikon(true);
+        });
+        while !RCC.cr().read().msikrdy() {}
+        msirange_to_hertz(range)
+    });
+
     let hsi = config.hsi.then(|| {
         RCC.cr().write(|w| w.set_hsion(true));
         while !RCC.cr().read().hsirdy() {}
@@ -181,7 +211,7 @@ pub(crate) unsafe fn init(config: Config) {
 
     let hsi48 = config.hsi48.map(super::init_hsi48);
 
-    let pll_input = PllInput { hse, hsi, msi };
+    let pll_input = PllInput { hse, hsi, msi: msis };
     let pll1 = init_pll(PllInstance::Pll1, config.pll1, &pll_input, config.voltage_range);
     let pll2 = init_pll(PllInstance::Pll2, config.pll2, &pll_input, config.voltage_range);
     let pll3 = init_pll(PllInstance::Pll3, config.pll3, &pll_input, config.voltage_range);
@@ -189,7 +219,7 @@ pub(crate) unsafe fn init(config: Config) {
     let sys_clk = match config.sys {
         Sysclk::HSE => hse.unwrap(),
         Sysclk::HSI => hsi.unwrap(),
-        Sysclk::MSIS => msi.unwrap(),
+        Sysclk::MSIS => msis.unwrap(),
         Sysclk::PLL1_R => pll1.r.unwrap(),
     };
 
@@ -276,6 +306,7 @@ pub(crate) unsafe fn init(config: Config) {
         pclk3: Some(pclk3),
         pclk1_tim: Some(pclk1_tim),
         pclk2_tim: Some(pclk2_tim),
+        msik: msik,
         hsi48: hsi48,
         rtc: rtc,
         hse: hse,
@@ -300,7 +331,6 @@ pub(crate) unsafe fn init(config: Config) {
         hsi48_div_2: None,
         lse: None,
         lsi: None,
-        msik: None,
         shsi: None,
         shsi_div_2: None,
     );