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Merge pull request #2677 from ExplodingWaffle/peri-clock

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stm32/rcc: wait for peripheral clock to be active. also, hold the peripheral reset while enabling the clock.
This commit is contained in:
Dario Nieuwenhuis 2024-03-18 16:23:28 +00:00 committed by GitHub
commit 6d9f87356b
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1 changed files with 25 additions and 17 deletions
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36
embassy-stm32/build.rs
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@ -509,25 +509,20 @@ fn main() {
if let Some(rcc) = &p.rcc {
let en = rcc.enable.as_ref().unwrap();
let rst = match &rcc.reset {
let (start_rst, end_rst) = match &rcc.reset {
Some(rst) => {
let rst_reg = format_ident!("{}", rst.register.to_ascii_lowercase());
let set_rst_field = format_ident!("set_{}", rst.field.to_ascii_lowercase());
(
quote! {
crate::pac::RCC.#rst_reg().modify(|w| w.#set_rst_field(true));
crate::pac::RCC.#rst_reg().modify(|w| w.#set_rst_field(false));
}
}
None => TokenStream::new(),
};
let after_enable = if chip_name.starts_with("stm32f2") {
// Errata: ES0005 - 2.1.11 Delay after an RCC peripheral clock enabling
},
quote! {
cortex_m::asm::dsb();
crate::pac::RCC.#rst_reg().modify(|w| w.#set_rst_field(false));
},
)
}
} else {
TokenStream::new()
None => (TokenStream::new(), TokenStream::new()),
};
let ptype = if let Some(reg) = &p.registers { reg.kind } else { "" };
@ -596,9 +591,22 @@ fn main() {
fn enable_and_reset_with_cs(_cs: critical_section::CriticalSection) {
#before_enable
#incr_stop_refcount
#start_rst
crate::pac::RCC.#en_reg().modify(|w| w.#set_en_field(true));
#after_enable
#rst
// we must wait two peripheral clock cycles before the clock is active
// this seems to work, but might be incorrect
// see http://efton.sk/STM32/gotcha/g183.html
// dummy read (like in the ST HALs)
let _ = crate::pac::RCC.#en_reg().read();
// DSB for good measure
cortex_m::asm::dsb();
#end_rst
}
fn disable_with_cs(_cs: critical_section::CriticalSection) {
#before_disable