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https://github.com/embassy-rs/embassy.git
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Merge pull request #2992 from liarokapisv/i2s-spi_v3
Add spi v3 & Full-duplex support to the I2S driver.
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
694ac3a515
@ -1,7 +1,9 @@
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//! Inter-IC Sound (I2S)
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use embassy_hal_internal::into_ref;
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use crate::gpio::{AFType, AnyPin, SealedPin};
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use crate::dma::ChannelAndRequest;
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use crate::gpio::{AFType, AnyPin, SealedPin, Speed};
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use crate::mode::Async;
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use crate::pac::spi::vals;
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use crate::spi::{Config as SpiConfig, *};
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@ -17,15 +19,6 @@ pub enum Mode {
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Slave,
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}
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/// I2S function
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#[derive(Copy, Clone)]
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pub enum Function {
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/// Transmit audio data
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Transmit,
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/// Receive audio data
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Receive,
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}
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/// I2C standard
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#[derive(Copy, Clone)]
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pub enum Standard {
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@ -42,7 +35,7 @@ pub enum Standard {
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}
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impl Standard {
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#[cfg(any(spi_v1, spi_f1))]
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#[cfg(any(spi_v1, spi_v3, spi_f1))]
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const fn i2sstd(&self) -> vals::I2sstd {
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match self {
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Standard::Philips => vals::I2sstd::PHILIPS,
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@ -53,7 +46,7 @@ impl Standard {
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}
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}
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#[cfg(any(spi_v1, spi_f1))]
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#[cfg(any(spi_v1, spi_v3, spi_f1))]
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const fn pcmsync(&self) -> vals::Pcmsync {
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match self {
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Standard::PcmLongSync => vals::Pcmsync::LONG,
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@ -76,7 +69,7 @@ pub enum Format {
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}
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impl Format {
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#[cfg(any(spi_v1, spi_f1))]
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#[cfg(any(spi_v1, spi_v3, spi_f1))]
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const fn datlen(&self) -> vals::Datlen {
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match self {
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Format::Data16Channel16 => vals::Datlen::BITS16,
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@ -86,7 +79,7 @@ impl Format {
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}
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}
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#[cfg(any(spi_v1, spi_f1))]
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#[cfg(any(spi_v1, spi_v3, spi_f1))]
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const fn chlen(&self) -> vals::Chlen {
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match self {
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Format::Data16Channel16 => vals::Chlen::BITS16,
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@ -107,7 +100,7 @@ pub enum ClockPolarity {
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}
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impl ClockPolarity {
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#[cfg(any(spi_v1, spi_f1))]
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#[cfg(any(spi_v1, spi_v3, spi_f1))]
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const fn ckpol(&self) -> vals::Ckpol {
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match self {
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ClockPolarity::IdleHigh => vals::Ckpol::IDLEHIGH,
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@ -127,15 +120,13 @@ impl ClockPolarity {
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pub struct Config {
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/// Mode
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pub mode: Mode,
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/// Function (transmit, receive)
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pub function: Function,
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/// Which I2S standard to use.
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pub standard: Standard,
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/// Data format.
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pub format: Format,
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/// Clock polarity.
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pub clock_polarity: ClockPolarity,
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/// True to eanble master clock output from this instance.
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/// True to enable master clock output from this instance.
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pub master_clock: bool,
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}
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@ -143,7 +134,6 @@ impl Default for Config {
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fn default() -> Self {
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Self {
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mode: Mode::Master,
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function: Function::Transmit,
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standard: Standard::Philips,
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format: Format::Data16Channel16,
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clock_polarity: ClockPolarity::IdleLow,
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@ -155,50 +145,168 @@ impl Default for Config {
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/// I2S driver.
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pub struct I2S<'d> {
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_peri: Spi<'d, Async>,
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sd: Option<PeripheralRef<'d, AnyPin>>,
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txsd: Option<PeripheralRef<'d, AnyPin>>,
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rxsd: Option<PeripheralRef<'d, AnyPin>>,
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ws: Option<PeripheralRef<'d, AnyPin>>,
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ck: Option<PeripheralRef<'d, AnyPin>>,
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mck: Option<PeripheralRef<'d, AnyPin>>,
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}
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/// I2S function
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#[derive(Copy, Clone)]
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#[allow(dead_code)]
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enum Function {
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/// Transmit audio data
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Transmit,
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/// Receive audio data
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Receive,
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#[cfg(spi_v3)]
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/// Transmit and Receive audio data
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FullDuplex,
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}
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impl<'d> I2S<'d> {
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/// Note: Full-Duplex modes are not supported at this time
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pub fn new<T: Instance>(
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/// Create a transmitter driver
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pub fn new_txonly<T: Instance>(
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peri: impl Peripheral<P = T> + 'd,
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sd: impl Peripheral<P = impl MosiPin<T>> + 'd,
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ws: impl Peripheral<P = impl WsPin<T>> + 'd,
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ck: impl Peripheral<P = impl CkPin<T>> + 'd,
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mck: impl Peripheral<P = impl MckPin<T>> + 'd,
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txdma: impl Peripheral<P = impl TxDma<T>> + 'd,
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freq: Hertz,
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config: Config,
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) -> Self {
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into_ref!(sd);
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Self::new_inner(
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peri,
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new_pin!(sd, AFType::OutputPushPull, Speed::VeryHigh),
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None,
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ws,
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ck,
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mck,
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new_dma!(txdma),
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None,
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freq,
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config,
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Function::Transmit,
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)
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}
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/// Create a receiver driver
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pub fn new_rxonly<T: Instance>(
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peri: impl Peripheral<P = T> + 'd,
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sd: impl Peripheral<P = impl MisoPin<T>> + 'd,
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ws: impl Peripheral<P = impl WsPin<T>> + 'd,
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ck: impl Peripheral<P = impl CkPin<T>> + 'd,
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mck: impl Peripheral<P = impl MckPin<T>> + 'd,
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#[cfg(not(spi_v3))] txdma: impl Peripheral<P = impl TxDma<T>> + 'd,
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rxdma: impl Peripheral<P = impl RxDma<T>> + 'd,
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freq: Hertz,
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config: Config,
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) -> Self {
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into_ref!(sd, ws, ck, mck);
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sd.set_as_af(sd.af_num(), AFType::OutputPushPull);
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sd.set_speed(crate::gpio::Speed::VeryHigh);
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ws.set_as_af(ws.af_num(), AFType::OutputPushPull);
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ws.set_speed(crate::gpio::Speed::VeryHigh);
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ck.set_as_af(ck.af_num(), AFType::OutputPushPull);
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ck.set_speed(crate::gpio::Speed::VeryHigh);
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mck.set_as_af(mck.af_num(), AFType::OutputPushPull);
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mck.set_speed(crate::gpio::Speed::VeryHigh);
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let mut spi_cfg = SpiConfig::default();
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spi_cfg.frequency = freq;
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let spi = Spi::new_internal(
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into_ref!(sd);
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Self::new_inner(
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peri,
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None,
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new_pin!(sd, AFType::OutputPushPull, Speed::VeryHigh),
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ws,
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ck,
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mck,
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#[cfg(not(spi_v3))]
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new_dma!(txdma),
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#[cfg(spi_v3)]
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None,
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new_dma!(rxdma),
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spi_cfg,
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);
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freq,
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config,
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#[cfg(not(spi_v3))]
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Function::Transmit,
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#[cfg(spi_v3)]
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Function::Receive,
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)
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}
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#[cfg(spi_v3)]
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/// Create a full duplex transmitter driver
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pub fn new_full_duplex<T: Instance>(
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peri: impl Peripheral<P = T> + 'd,
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txsd: impl Peripheral<P = impl MosiPin<T>> + 'd,
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rxsd: impl Peripheral<P = impl MisoPin<T>> + 'd,
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ws: impl Peripheral<P = impl WsPin<T>> + 'd,
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ck: impl Peripheral<P = impl CkPin<T>> + 'd,
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mck: impl Peripheral<P = impl MckPin<T>> + 'd,
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txdma: impl Peripheral<P = impl TxDma<T>> + 'd,
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rxdma: impl Peripheral<P = impl RxDma<T>> + 'd,
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freq: Hertz,
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config: Config,
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) -> Self {
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into_ref!(txsd, rxsd);
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Self::new_inner(
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peri,
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new_pin!(txsd, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(rxsd, AFType::OutputPushPull, Speed::VeryHigh),
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ws,
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ck,
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mck,
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new_dma!(txdma),
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new_dma!(rxdma),
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freq,
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config,
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Function::FullDuplex,
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)
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}
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/// Write audio data.
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pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
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self._peri.read(data).await
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}
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/// Write audio data.
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pub async fn write<W: Word>(&mut self, data: &[W]) -> Result<(), Error> {
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self._peri.write(data).await
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}
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/// Transfer audio data.
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pub async fn transfer<W: Word>(&mut self, read: &mut [W], write: &[W]) -> Result<(), Error> {
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self._peri.transfer(read, write).await
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}
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/// Transfer audio data in place.
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pub async fn transfer_in_place<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
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self._peri.transfer_in_place(data).await
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}
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fn new_inner<T: Instance>(
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peri: impl Peripheral<P = T> + 'd,
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txsd: Option<PeripheralRef<'d, AnyPin>>,
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rxsd: Option<PeripheralRef<'d, AnyPin>>,
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ws: impl Peripheral<P = impl WsPin<T>> + 'd,
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ck: impl Peripheral<P = impl CkPin<T>> + 'd,
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mck: impl Peripheral<P = impl MckPin<T>> + 'd,
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txdma: Option<ChannelAndRequest<'d>>,
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rxdma: Option<ChannelAndRequest<'d>>,
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freq: Hertz,
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config: Config,
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function: Function,
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) -> Self {
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into_ref!(ws, ck, mck);
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ws.set_as_af(ws.af_num(), AFType::OutputPushPull);
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ws.set_speed(Speed::VeryHigh);
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ck.set_as_af(ck.af_num(), AFType::OutputPushPull);
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ck.set_speed(Speed::VeryHigh);
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mck.set_as_af(mck.af_num(), AFType::OutputPushPull);
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mck.set_speed(Speed::VeryHigh);
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let mut spi_cfg = SpiConfig::default();
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spi_cfg.frequency = freq;
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let spi = Spi::new_internal(peri, txdma, rxdma, spi_cfg);
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let regs = T::info().regs;
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// TODO move i2s to the new mux infra.
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//#[cfg(all(rcc_f4, not(stm32f410)))]
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@ -208,26 +316,23 @@ impl<'d> I2S<'d> {
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let (odd, div) = compute_baud_rate(pclk, freq, config.master_clock, config.format);
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#[cfg(any(spi_v1, spi_f1))]
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#[cfg(any(spi_v1, spi_v3, spi_f1))]
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{
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#[cfg(spi_v3)]
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{
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regs.cr1().modify(|w| w.set_spe(false));
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reset_incompatible_bitfields::<T>();
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}
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use stm32_metapac::spi::vals::{I2scfg, Odd};
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// 1. Select the I2SDIV[7:0] bits in the SPI_I2SPR register to define the serial clock baud
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// rate to reach the proper audio sample frequency. The ODD bit in the SPI_I2SPR
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// register also has to be defined.
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spi.info.regs.i2spr().modify(|w| {
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w.set_i2sdiv(div);
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w.set_odd(match odd {
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true => Odd::ODD,
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false => Odd::EVEN,
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});
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w.set_mckoe(config.master_clock);
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});
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// 1. Select the I2SDIV[7:0] bits in the SPI_I2SPR/SPI_I2SCFGR register to define the serial clock baud
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// rate to reach the proper audio sample frequency. The ODD bit in the
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// SPI_I2SPR/SPI_I2SCFGR register also has to be defined.
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// 2. Select the CKPOL bit to define the steady level for the communication clock. Set the
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// MCKOE bit in the SPI_I2SPR register if the master clock MCK needs to be provided to
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// MCKOE bit in the SPI_I2SPR/SPI_I2SCFGR register if the master clock MCK needs to be provided to
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// the external DAC/ADC audio component (the I2SDIV and ODD values should be
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// computed depending on the state of the MCK output, for more details refer to
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// Section 28.4.4: Clock generator).
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@ -243,50 +348,72 @@ impl<'d> I2S<'d> {
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// 5. The I2SE bit in SPI_I2SCFGR register must be set.
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spi.info.regs.i2scfgr().modify(|w| {
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let clk_reg = {
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#[cfg(any(spi_v1, spi_f1))]
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{
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regs.i2spr()
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}
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#[cfg(spi_v3)]
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{
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regs.i2scfgr()
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}
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};
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clk_reg.modify(|w| {
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w.set_i2sdiv(div);
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w.set_odd(match odd {
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true => Odd::ODD,
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false => Odd::EVEN,
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});
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w.set_mckoe(config.master_clock);
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});
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regs.i2scfgr().modify(|w| {
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w.set_ckpol(config.clock_polarity.ckpol());
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w.set_i2smod(true);
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w.set_i2sstd(config.standard.i2sstd());
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w.set_pcmsync(config.standard.pcmsync());
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w.set_datlen(config.format.datlen());
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w.set_chlen(config.format.chlen());
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w.set_i2scfg(match (config.mode, config.function) {
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w.set_i2scfg(match (config.mode, function) {
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(Mode::Master, Function::Transmit) => I2scfg::MASTERTX,
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(Mode::Master, Function::Receive) => I2scfg::MASTERRX,
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#[cfg(spi_v3)]
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(Mode::Master, Function::FullDuplex) => I2scfg::MASTERFULLDUPLEX,
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(Mode::Slave, Function::Transmit) => I2scfg::SLAVETX,
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(Mode::Slave, Function::Receive) => I2scfg::SLAVERX,
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#[cfg(spi_v3)]
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(Mode::Slave, Function::FullDuplex) => I2scfg::SLAVEFULLDUPLEX,
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});
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w.set_i2se(true)
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#[cfg(any(spi_v1, spi_f1))]
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w.set_i2se(true);
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});
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#[cfg(spi_v3)]
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regs.cr1().modify(|w| w.set_spe(true));
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}
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Self {
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_peri: spi,
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sd: Some(sd.map_into()),
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txsd: txsd.map(|w| w.map_into()),
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rxsd: rxsd.map(|w| w.map_into()),
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ws: Some(ws.map_into()),
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ck: Some(ck.map_into()),
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mck: Some(mck.map_into()),
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}
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}
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/// Write audio data.
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pub async fn write<W: Word>(&mut self, data: &[W]) -> Result<(), Error> {
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self._peri.write(data).await
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}
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/// Read audio data.
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pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
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self._peri.read(data).await
|
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}
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}
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impl<'d> Drop for I2S<'d> {
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fn drop(&mut self) {
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self.sd.as_ref().map(|x| x.set_as_disconnected());
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self.txsd.as_ref().map(|x| x.set_as_disconnected());
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self.rxsd.as_ref().map(|x| x.set_as_disconnected());
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self.ws.as_ref().map(|x| x.set_as_disconnected());
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self.ck.as_ref().map(|x| x.set_as_disconnected());
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self.mck.as_ref().map(|x| x.set_as_disconnected());
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@ -328,3 +455,71 @@ fn compute_baud_rate(i2s_clock: Hertz, request_freq: Hertz, mclk: bool, data_for
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((division & 1) == 1, (division >> 1) as u8)
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}
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}
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#[cfg(spi_v3)]
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// The STM32H7 reference manual specifies that any incompatible bitfields should be reset
|
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// to their reset values while operating in I2S mode.
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fn reset_incompatible_bitfields<T: Instance>() {
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let regs = T::info().regs;
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regs.cr1().modify(|w| {
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let iolock = w.iolock();
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let csusp = w.csusp();
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let spe = w.cstart();
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let cstart = w.cstart();
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w.0 = 0;
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w.set_iolock(iolock);
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w.set_csusp(csusp);
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w.set_spe(spe);
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w.set_cstart(cstart);
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});
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regs.cr2().write(|w| w.0 = 0);
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regs.cfg1().modify(|w| {
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let txdmaen = w.txdmaen();
|
||||
let rxdmaen = w.rxdmaen();
|
||||
let fthlv = w.fthlv();
|
||||
w.0 = 0;
|
||||
w.set_txdmaen(txdmaen);
|
||||
w.set_rxdmaen(rxdmaen);
|
||||
w.set_fthlv(fthlv);
|
||||
});
|
||||
|
||||
regs.cfg2().modify(|w| {
|
||||
let afcntr = w.afcntr();
|
||||
let lsbfirst = w.lsbfirst();
|
||||
let ioswp = w.ioswp();
|
||||
w.0 = 0;
|
||||
w.set_afcntr(afcntr);
|
||||
w.set_lsbfirst(lsbfirst);
|
||||
w.set_ioswp(ioswp);
|
||||
});
|
||||
|
||||
regs.ier().modify(|w| {
|
||||
let tifreie = w.tifreie();
|
||||
let ovrie = w.ovrie();
|
||||
let udrie = w.udrie();
|
||||
let txpie = w.txpie();
|
||||
let rxpie = w.rxpie();
|
||||
|
||||
w.0 = 0;
|
||||
|
||||
w.set_tifreie(tifreie);
|
||||
w.set_ovrie(ovrie);
|
||||
w.set_udrie(udrie);
|
||||
w.set_txpie(txpie);
|
||||
w.set_rxpie(rxpie);
|
||||
});
|
||||
|
||||
regs.ifcr().write(|w| {
|
||||
w.set_suspc(true);
|
||||
w.set_tifrec(true);
|
||||
w.set_ovrc(true);
|
||||
w.set_udrc(true);
|
||||
});
|
||||
|
||||
regs.crcpoly().write(|w| w.0 = 0x107);
|
||||
regs.txcrc().write(|w| w.0 = 0);
|
||||
regs.rxcrc().write(|w| w.0 = 0);
|
||||
regs.udrdr().write(|w| w.0 = 0);
|
||||
}
|
||||
|
||||
@ -83,7 +83,7 @@ pub mod hrtim;
|
||||
pub mod hsem;
|
||||
#[cfg(i2c)]
|
||||
pub mod i2c;
|
||||
#[cfg(all(spi_v1, rcc_f4))]
|
||||
#[cfg(any(all(spi_v1, rcc_f4), spi_v3))]
|
||||
pub mod i2s;
|
||||
#[cfg(stm32wb)]
|
||||
pub mod ipcc;
|
||||
|
||||
@ -15,14 +15,13 @@ async fn main(_spawner: Spawner) {
|
||||
let p = embassy_stm32::init(Default::default());
|
||||
info!("Hello World!");
|
||||
|
||||
let mut i2s = I2S::new(
|
||||
let mut i2s = I2S::new_txonly(
|
||||
p.SPI2,
|
||||
p.PC3, // sd
|
||||
p.PB12, // ws
|
||||
p.PB10, // ck
|
||||
p.PC6, // mck
|
||||
p.DMA1_CH4,
|
||||
p.DMA1_CH3,
|
||||
Hertz(1_000_000),
|
||||
Config::default(),
|
||||
);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user