nordic-dev.net/embassy
2
0
Fork 0
mirror of https://github.com/embassy-rs/embassy.git synced 2024-11-21 22:32:29 +00:00
Code Issues Packages Projects Releases Wiki Activity

remove trailing spaces

Browse Source
This commit is contained in:
Riley Williams 2023-10-17 19:30:53 -04:00
parent cb211f88d3
commit 6906cc9c25
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
embassy-rp/src/pwm.rs
View File

@ -33,15 +33,15 @@ pub struct Config {
/// A higher value will result in a slower output frequency. /// A higher value will result in a slower output frequency.
pub divider: fixed::FixedU16<fixed::types::extra::U4>, pub divider: fixed::FixedU16<fixed::types::extra::U4>,
/// The output on channel A goes high when `compare_a` is higher than the /// The output on channel A goes high when `compare_a` is higher than the
/// counter. A compare of 0 will produce an always low output, while a /// counter. A compare of 0 will produce an always low output, while a
/// compare of `top + 1` will produce an always high output. /// compare of `top + 1` will produce an always high output.
pub compare_a: u16, pub compare_a: u16,
/// The output on channel B goes high when `compare_b` is higher than the /// The output on channel B goes high when `compare_b` is higher than the
/// counter. A compare of 0 will produce an always low output, while a /// counter. A compare of 0 will produce an always low output, while a
/// compare of `top + 1` will produce an always high output. /// compare of `top + 1` will produce an always high output.
pub compare_b: u16, pub compare_b: u16,
/// The point at which the counter wraps, representing the maximum possible /// The point at which the counter wraps, representing the maximum possible
/// period. The counter will either wrap to 0 or reverse depending on the /// period. The counter will either wrap to 0 or reverse depending on the
/// setting of `phase_correct`. /// setting of `phase_correct`.
pub top: u16, pub top: u16,
} }
@ -196,8 +196,8 @@ impl<'d, T: Channel> Pwm<'d, T> {
}); });
} }
/// Advances a slice’s output phase by one count while it is running /// Advances a slice’s output phase by one count while it is running
/// by inserting a pulse into the clock enable. The counter /// by inserting a pulse into the clock enable. The counter
/// will not count faster than once per cycle. /// will not count faster than once per cycle.
#[inline] #[inline]
pub fn phase_advance(&mut self) { pub fn phase_advance(&mut self) {
@ -206,7 +206,7 @@ impl<'d, T: Channel> Pwm<'d, T> {
while p.csr().read().ph_adv() {} while p.csr().read().ph_adv() {}
} }
/// Retards a slice’s output phase by one count while it is running /// Retards a slice’s output phase by one count while it is running
/// by deleting a pulse from the clock enable. The counter will not /// by deleting a pulse from the clock enable. The counter will not
/// count backward when clock enable is permenantly low. /// count backward when clock enable is permenantly low.
#[inline] #[inline]