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https://github.com/embassy-rs/embassy.git
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Call set_word_size
before disabling SPE
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parent
3ae0923d45
commit
683c11f399
@ -10,12 +10,12 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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where
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Tx: TxDma<T>,
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{
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self.set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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self.set_word_size(WordSize::EightBit);
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let tx_request = self.txdma.request();
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let tx_dst = T::regs().tx_ptr();
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@ -43,6 +43,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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Tx: TxDma<T>,
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Rx: RxDma<T>,
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{
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self.set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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@ -51,7 +52,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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reg.set_rxdmaen(true);
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});
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}
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self.set_word_size(WordSize::EightBit);
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let (_, clock_byte_count) = slice_ptr_parts_mut(read);
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@ -100,6 +100,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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let (_, tx_len) = slice_ptr_parts(write);
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assert_eq!(rx_len, tx_len);
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self.set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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@ -108,7 +109,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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reg.set_rxdmaen(true);
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});
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}
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self.set_word_size(WordSize::EightBit);
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let rx_request = self.rxdma.request();
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let rx_src = T::regs().rx_ptr();
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@ -10,6 +10,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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where
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Tx: TxDma<T>,
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{
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self.set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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@ -20,7 +21,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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let _ = T::regs().dr().read();
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}
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}
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self.set_word_size(WordSize::EightBit);
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let tx_request = self.txdma.request();
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let tx_dst = T::regs().tx_ptr();
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@ -48,6 +48,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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Tx: TxDma<T>,
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Rx: RxDma<T>,
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{
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self.set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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@ -56,7 +57,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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reg.set_rxdmaen(true);
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});
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}
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self.set_word_size(WordSize::EightBit);
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let (_, clock_byte_count) = slice_ptr_parts_mut(read);
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@ -105,6 +105,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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let (_, tx_len) = slice_ptr_parts(write);
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assert_eq!(rx_len, tx_len);
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self.set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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@ -118,7 +119,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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let _ = T::regs().dr().read();
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}
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}
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self.set_word_size(WordSize::EightBit);
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let rx_request = self.rxdma.request();
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let rx_src = T::regs().rx_ptr();
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