diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs index 2c620798d..fb72422bd 100644 --- a/embassy-nrf/src/buffered_uarte.rs +++ b/embassy-nrf/src/buffered_uarte.rs @@ -377,7 +377,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> { }); // Enable UARTE instance - apply_workaround_for_enable_anomaly(&r); + apply_workaround_for_enable_anomaly(r); r.enable.write(|w| w.enable().enabled()); // Configure byte counter. diff --git a/embassy-nrf/src/nvmc.rs b/embassy-nrf/src/nvmc.rs index de840b886..4f9eda167 100644 --- a/embassy-nrf/src/nvmc.rs +++ b/embassy-nrf/src/nvmc.rs @@ -160,7 +160,7 @@ impl<'d> NorFlash for Nvmc<'d> { if offset as usize + bytes.len() > FLASH_SIZE { return Err(Error::OutOfBounds); } - if offset as usize % 4 != 0 || bytes.len() as usize % 4 != 0 { + if offset as usize % 4 != 0 || bytes.len() % 4 != 0 { return Err(Error::Unaligned); } diff --git a/embassy-nrf/src/pdm.rs b/embassy-nrf/src/pdm.rs index 6ddc4dc0a..754d38310 100644 --- a/embassy-nrf/src/pdm.rs +++ b/embassy-nrf/src/pdm.rs @@ -185,7 +185,7 @@ impl<'d, T: Instance> Pdm<'d, T> { /// Sample data into the given buffer pub async fn sample(&mut self, buffer: &mut [i16]) -> Result<(), Error> { - if buffer.len() == 0 { + if buffer.is_empty() { return Err(Error::BufferZeroLength); } if buffer.len() > EASY_DMA_SIZE { diff --git a/embassy-nrf/src/pwm.rs b/embassy-nrf/src/pwm.rs index e0583b770..833370d4b 100644 --- a/embassy-nrf/src/pwm.rs +++ b/embassy-nrf/src/pwm.rs @@ -444,7 +444,7 @@ impl<'d, 's, T: Instance> Sequencer<'d, 's, T> { return Err(Error::SequenceTimesAtLeastOne); } - let _ = self.stop(); + self.stop(); let r = T::regs(); @@ -507,7 +507,7 @@ impl<'d, 's, T: Instance> Sequencer<'d, 's, T> { impl<'d, 's, T: Instance> Drop for Sequencer<'d, 's, T> { fn drop(&mut self) { - let _ = self.stop(); + self.stop(); } } @@ -697,7 +697,7 @@ impl<'d, T: Instance> SimplePwm<'d, T> { // Enable r.enable.write(|w| w.enable().enabled()); - r.seq0.ptr.write(|w| unsafe { w.bits((&pwm.duty).as_ptr() as u32) }); + r.seq0.ptr.write(|w| unsafe { w.bits((pwm.duty).as_ptr() as u32) }); r.seq0.cnt.write(|w| unsafe { w.bits(4) }); r.seq0.refresh.write(|w| unsafe { w.bits(0) }); @@ -748,7 +748,7 @@ impl<'d, T: Instance> SimplePwm<'d, T> { self.duty[channel] = duty & 0x7FFF; // reload ptr in case self was moved - r.seq0.ptr.write(|w| unsafe { w.bits((&self.duty).as_ptr() as u32) }); + r.seq0.ptr.write(|w| unsafe { w.bits((self.duty).as_ptr() as u32) }); // defensive before seqstart compiler_fence(Ordering::SeqCst); diff --git a/embassy-nrf/src/qdec.rs b/embassy-nrf/src/qdec.rs index 2aa50a2ba..9455ec925 100644 --- a/embassy-nrf/src/qdec.rs +++ b/embassy-nrf/src/qdec.rs @@ -172,18 +172,17 @@ impl<'d, T: Instance> Qdec<'d, T> { t.intenset.write(|w| w.reportrdy().set()); unsafe { t.tasks_readclracc.write(|w| w.bits(1)) }; - let value = poll_fn(|cx| { + poll_fn(|cx| { T::state().waker.register(cx.waker()); if t.events_reportrdy.read().bits() == 0 { - return Poll::Pending; + Poll::Pending } else { t.events_reportrdy.reset(); let acc = t.accread.read().bits(); Poll::Ready(acc as i16) } }) - .await; - value + .await } } diff --git a/embassy-nrf/src/qspi.rs b/embassy-nrf/src/qspi.rs index 8eec09c96..4134a4c87 100755 --- a/embassy-nrf/src/qspi.rs +++ b/embassy-nrf/src/qspi.rs @@ -402,7 +402,7 @@ impl<'d, T: Instance> Qspi<'d, T> { /// a raw bus, not with flash memory. pub async fn read_raw(&mut self, address: u32, data: &mut [u8]) -> Result<(), Error> { // Avoid blocking_wait_ready() blocking forever on zero-length buffers. - if data.len() == 0 { + if data.is_empty() { return Ok(()); } @@ -423,7 +423,7 @@ impl<'d, T: Instance> Qspi<'d, T> { /// a raw bus, not with flash memory. pub async fn write_raw(&mut self, address: u32, data: &[u8]) -> Result<(), Error> { // Avoid blocking_wait_ready() blocking forever on zero-length buffers. - if data.len() == 0 { + if data.is_empty() { return Ok(()); } @@ -444,7 +444,7 @@ impl<'d, T: Instance> Qspi<'d, T> { /// a raw bus, not with flash memory. pub fn blocking_read_raw(&mut self, address: u32, data: &mut [u8]) -> Result<(), Error> { // Avoid blocking_wait_ready() blocking forever on zero-length buffers. - if data.len() == 0 { + if data.is_empty() { return Ok(()); } @@ -460,7 +460,7 @@ impl<'d, T: Instance> Qspi<'d, T> { /// a raw bus, not with flash memory. pub fn blocking_write_raw(&mut self, address: u32, data: &[u8]) -> Result<(), Error> { // Avoid blocking_wait_ready() blocking forever on zero-length buffers. - if data.len() == 0 { + if data.is_empty() { return Ok(()); } diff --git a/embassy-nrf/src/rng.rs b/embassy-nrf/src/rng.rs index 40b73231b..1c463fb7c 100644 --- a/embassy-nrf/src/rng.rs +++ b/embassy-nrf/src/rng.rs @@ -108,7 +108,7 @@ impl<'d, T: Instance> Rng<'d, T> { /// Fill the buffer with random bytes. pub async fn fill_bytes(&mut self, dest: &mut [u8]) { - if dest.len() == 0 { + if dest.is_empty() { return; // Nothing to fill } diff --git a/embassy-nrf/src/temp.rs b/embassy-nrf/src/temp.rs index 5e2998b10..ed4a47713 100644 --- a/embassy-nrf/src/temp.rs +++ b/embassy-nrf/src/temp.rs @@ -83,7 +83,7 @@ impl<'d> Temp<'d> { let value = poll_fn(|cx| { WAKER.register(cx.waker()); if t.events_datardy.read().bits() == 0 { - return Poll::Pending; + Poll::Pending } else { t.events_datardy.reset(); let raw = t.temp.read().bits(); diff --git a/embassy-nrf/src/twim.rs b/embassy-nrf/src/twim.rs index da8e15d02..24810a08c 100644 --- a/embassy-nrf/src/twim.rs +++ b/embassy-nrf/src/twim.rs @@ -372,7 +372,7 @@ impl<'d, T: Instance> Twim<'d, T> { // Start write operation. r.shorts.write(|w| w.lasttx_stop().enabled()); r.tasks_starttx.write(|w| unsafe { w.bits(1) }); - if buffer.len() == 0 { + if buffer.is_empty() { // With a zero-length buffer, LASTTX doesn't fire (because there's no last byte!), so do the STOP ourselves. r.tasks_stop.write(|w| unsafe { w.bits(1) }); } @@ -403,7 +403,7 @@ impl<'d, T: Instance> Twim<'d, T> { // Start read operation. r.shorts.write(|w| w.lastrx_stop().enabled()); r.tasks_startrx.write(|w| unsafe { w.bits(1) }); - if buffer.len() == 0 { + if buffer.is_empty() { // With a zero-length buffer, LASTRX doesn't fire (because there's no last byte!), so do the STOP ourselves. r.tasks_stop.write(|w| unsafe { w.bits(1) }); } @@ -447,7 +447,7 @@ impl<'d, T: Instance> Twim<'d, T> { w }); r.tasks_starttx.write(|w| unsafe { w.bits(1) }); - if wr_buffer.len() == 0 && rd_buffer.len() == 0 { + if wr_buffer.is_empty() && rd_buffer.is_empty() { // With a zero-length buffer, LASTRX/LASTTX doesn't fire (because there's no last byte!), so do the STOP ourselves. // TODO handle when only one of the buffers is zero length r.tasks_stop.write(|w| unsafe { w.bits(1) }); @@ -469,7 +469,7 @@ impl<'d, T: Instance> Twim<'d, T> { trace!("Copying TWIM tx buffer into RAM for DMA"); let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()]; tx_ram_buf.copy_from_slice(wr_buffer); - self.setup_write_read_from_ram(address, &tx_ram_buf, rd_buffer, inten) + self.setup_write_read_from_ram(address, tx_ram_buf, rd_buffer, inten) } Err(error) => Err(error), } @@ -482,7 +482,7 @@ impl<'d, T: Instance> Twim<'d, T> { trace!("Copying TWIM tx buffer into RAM for DMA"); let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()]; tx_ram_buf.copy_from_slice(wr_buffer); - self.setup_write_from_ram(address, &tx_ram_buf, inten) + self.setup_write_from_ram(address, tx_ram_buf, inten) } Err(error) => Err(error), } @@ -779,7 +779,7 @@ mod eh02 { impl<'a, T: Instance> embedded_hal_02::blocking::i2c::Write for Twim<'a, T> { type Error = Error; - fn write<'w>(&mut self, addr: u8, bytes: &'w [u8]) -> Result<(), Error> { + fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> { if slice_in_ram(bytes) { self.blocking_write(addr, bytes) } else { @@ -796,7 +796,7 @@ mod eh02 { impl<'a, T: Instance> embedded_hal_02::blocking::i2c::Read for Twim<'a, T> { type Error = Error; - fn read<'w>(&mut self, addr: u8, bytes: &'w mut [u8]) -> Result<(), Error> { + fn read(&mut self, addr: u8, bytes: &mut [u8]) -> Result<(), Error> { self.blocking_read(addr, bytes) } } @@ -847,10 +847,10 @@ impl<'d, T: Instance> embedded_hal_1::i2c::I2c for Twim<'d, T> { self.blocking_write_read(address, wr_buffer, rd_buffer) } - fn transaction<'a>( + fn transaction( &mut self, _address: u8, - _operations: &mut [embedded_hal_1::i2c::Operation<'a>], + _operations: &mut [embedded_hal_1::i2c::Operation<'_>], ) -> Result<(), Self::Error> { todo!(); } diff --git a/embassy-nrf/src/twis.rs b/embassy-nrf/src/twis.rs index c6c020557..415150447 100644 --- a/embassy-nrf/src/twis.rs +++ b/embassy-nrf/src/twis.rs @@ -577,7 +577,7 @@ impl<'d, T: Instance> Twis<'d, T> { trace!("Copying TWIS tx buffer into RAM for DMA"); let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()]; tx_ram_buf.copy_from_slice(wr_buffer); - self.setup_respond_from_ram(&tx_ram_buf, inten) + self.setup_respond_from_ram(tx_ram_buf, inten) } Err(error) => Err(error), } diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs index de2966ba5..9e5b85dea 100644 --- a/embassy-nrf/src/uarte.rs +++ b/embassy-nrf/src/uarte.rs @@ -308,7 +308,7 @@ fn configure(r: &RegisterBlock, config: Config, hardware_flow_control: bool) { r.events_txstarted.reset(); // Enable - apply_workaround_for_enable_anomaly(&r); + apply_workaround_for_enable_anomaly(r); r.enable.write(|w| w.enable().enabled()); } @@ -378,7 +378,7 @@ impl<'d, T: Instance> UarteTx<'d, T> { trace!("Copying UARTE tx buffer into RAM for DMA"); let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()]; ram_buf.copy_from_slice(buffer); - self.write_from_ram(&ram_buf).await + self.write_from_ram(ram_buf).await } Err(error) => Err(error), } @@ -386,7 +386,7 @@ impl<'d, T: Instance> UarteTx<'d, T> { /// Same as [`write`](Self::write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more. pub async fn write_from_ram(&mut self, buffer: &[u8]) -> Result<(), Error> { - if buffer.len() == 0 { + if buffer.is_empty() { return Ok(()); } @@ -448,7 +448,7 @@ impl<'d, T: Instance> UarteTx<'d, T> { trace!("Copying UARTE tx buffer into RAM for DMA"); let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()]; ram_buf.copy_from_slice(buffer); - self.blocking_write_from_ram(&ram_buf) + self.blocking_write_from_ram(ram_buf) } Err(error) => Err(error), } @@ -456,7 +456,7 @@ impl<'d, T: Instance> UarteTx<'d, T> { /// Same as [`write_from_ram`](Self::write_from_ram) but will fail instead of copying data into RAM. Consult the module level documentation to learn more. pub fn blocking_write_from_ram(&mut self, buffer: &[u8]) -> Result<(), Error> { - if buffer.len() == 0 { + if buffer.is_empty() { return Ok(()); } @@ -504,7 +504,7 @@ impl<'a, T: Instance> Drop for UarteTx<'a, T> { let s = T::state(); - drop_tx_rx(&r, &s); + drop_tx_rx(r, s); } } @@ -619,7 +619,7 @@ impl<'d, T: Instance> UarteRx<'d, T> { UarteRxWithIdle { rx: self, timer, - ppi_ch1: ppi_ch1, + ppi_ch1, _ppi_ch2: ppi_ch2, } } @@ -694,7 +694,7 @@ impl<'d, T: Instance> UarteRx<'d, T> { /// Read bytes until the buffer is filled. pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> { - if buffer.len() == 0 { + if buffer.is_empty() { return Ok(()); } if buffer.len() > EASY_DMA_SIZE { @@ -744,7 +744,7 @@ impl<'a, T: Instance> Drop for UarteRx<'a, T> { let s = T::state(); - drop_tx_rx(&r, &s); + drop_tx_rx(r, s); } } @@ -775,7 +775,7 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> { /// /// Returns the amount of bytes read. pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result { - if buffer.len() == 0 { + if buffer.is_empty() { return Ok(0); } if buffer.len() > EASY_DMA_SIZE { @@ -848,7 +848,7 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> { /// /// Returns the amount of bytes read. pub fn blocking_read_until_idle(&mut self, buffer: &mut [u8]) -> Result { - if buffer.len() == 0 { + if buffer.is_empty() { return Ok(0); } if buffer.len() > EASY_DMA_SIZE {