From 5cba97821f6f3e716452d38bb0c645b51592abc0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=ABl=20Schulz-Ansres?= Date: Fri, 24 May 2024 01:05:56 +0200 Subject: [PATCH] Naming: Change pullup to pull --- embassy-stm32/src/spi/mod.rs | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs index 9238e0f6f..5fc8691ac 100644 --- a/embassy-stm32/src/spi/mod.rs +++ b/embassy-stm32/src/spi/mod.rs @@ -54,7 +54,7 @@ pub struct Config { /// /// There are some ICs that require a pull-up on the MISO pin for some applications. /// If you are unsure, you probably don't need this. - pub miso_pullup: Pull, + pub miso_pull: Pull, } impl Default for Config { @@ -63,7 +63,7 @@ impl Default for Config { mode: MODE_0, bit_order: BitOrder::MsbFirst, frequency: Hertz(1_000_000), - miso_pullup: Pull::None, + miso_pull: Pull::None, } } } @@ -279,7 +279,7 @@ impl<'d, M: PeriMode> Spi<'d, M> { BitOrder::MsbFirst }; - let miso_pullup = match &self.miso { + let miso_pull = match &self.miso { None => Pull::None, Some(pin) => pin.pull(), }; @@ -295,7 +295,7 @@ impl<'d, M: PeriMode> Spi<'d, M> { mode: Mode { polarity, phase }, bit_order, frequency, - miso_pullup, + miso_pull, } } @@ -418,7 +418,7 @@ impl<'d> Spi<'d, Blocking> { peri, new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()), new_pin!(mosi, AFType::OutputPushPull, Speed::VeryHigh), - new_pin!(miso, AFType::Input, Speed::VeryHigh, config.miso_pullup), + new_pin!(miso, AFType::Input, Speed::VeryHigh, config.miso_pull), None, None, config, @@ -436,7 +436,7 @@ impl<'d> Spi<'d, Blocking> { peri, new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()), None, - new_pin!(miso, AFType::Input, Speed::VeryHigh, config.miso_pullup), + new_pin!(miso, AFType::Input, Speed::VeryHigh, config.miso_pull), None, None, config,