mirror of
https://github.com/embassy-rs/embassy.git
synced 2024-11-27 01:02:37 +00:00
commit
5bd0aa9cb5
@ -196,8 +196,9 @@ impl<'d, T: Instance> FullDuplex<u8> for Spim<'d, T> {
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fn read_write<'a>(&'a mut self, rx: &'a mut [u8], tx: &'a [u8]) -> Self::WriteReadFuture<'a> {
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async move {
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slice_in_ram_or(rx, Error::DMABufferNotInDataMemory)?;
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slice_in_ram_or(tx, Error::DMABufferNotInDataMemory)?;
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// NOTE: RAM slice check for rx is not necessary, as a mutable
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// slice can only be built from data located in RAM.
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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@ -6,11 +6,16 @@
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//!
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//! - nRF52832: Section 33
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//! - nRF52840: Section 6.31
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use core::future::Future;
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use core::marker::PhantomData;
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use core::sync::atomic::{compiler_fence, Ordering::SeqCst};
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use core::task::Poll;
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use embassy::interrupt::{Interrupt, InterruptExt};
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use embassy::traits;
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use embassy::util::{AtomicWaker, Unborrow};
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use embassy_extras::unborrow;
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use futures::future::poll_fn;
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use traits::i2c::I2c;
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use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
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use crate::gpio::Pin as GpioPin;
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@ -418,6 +423,26 @@ impl<'d, T: Instance> Twim<'d, T> {
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self.write_then_read(address, wr_ram_buffer, rd_buffer)
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}
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fn wait_for_stopped_event(cx: &mut core::task::Context) -> Poll<()> {
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let r = T::regs();
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let s = T::state();
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s.end_waker.register(cx.waker());
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if r.events_stopped.read().bits() != 0 {
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r.events_stopped.reset();
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return Poll::Ready(());
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}
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// stop if an error occured
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if r.events_error.read().bits() != 0 {
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r.events_error.reset();
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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}
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Poll::Pending
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}
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}
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impl<'a, T: Instance> Drop for Twim<'a, T> {
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@ -437,6 +462,191 @@ impl<'a, T: Instance> Drop for Twim<'a, T> {
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}
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}
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impl<'d, T> I2c for Twim<'d, T>
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where
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T: Instance,
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{
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type Error = Error;
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#[rustfmt::skip]
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type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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#[rustfmt::skip]
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type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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#[rustfmt::skip]
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type WriteReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> {
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async move {
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// NOTE: RAM slice check for buffer is not necessary, as a mutable
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// slice can only be built from data located in RAM.
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let r = T::regs();
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// before any DMA action has started.
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compiler_fence(SeqCst);
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r.address.write(|w| unsafe { w.address().bits(address) });
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// Set up the DMA read.
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unsafe { self.set_rx_buffer(buffer)? };
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// Reset events
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r.events_stopped.reset();
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r.events_error.reset();
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self.clear_errorsrc();
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// Enable events
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r.intenset.write(|w| w.stopped().set().error().set());
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// Start read operation.
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r.shorts.write(|w| w.lastrx_stop().enabled());
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r.tasks_startrx.write(|w|
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// `1` is a valid value to write to task registers.
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unsafe { w.bits(1) });
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// after all possible DMA actions have completed.
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compiler_fence(SeqCst);
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// Wait for 'stopped' event.
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poll_fn(Self::wait_for_stopped_event).await;
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self.read_errorsrc()?;
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if r.rxd.amount.read().bits() != buffer.len() as u32 {
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return Err(Error::Receive);
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}
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Ok(())
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}
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}
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fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Self::WriteFuture<'a> {
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async move {
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slice_in_ram_or(bytes, Error::DMABufferNotInDataMemory)?;
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// before any DMA action has started.
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compiler_fence(SeqCst);
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let r = T::regs();
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// Set up current address we're trying to talk to
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r.address.write(|w| unsafe { w.address().bits(address) });
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// Set up DMA write.
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unsafe {
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self.set_tx_buffer(bytes)?;
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}
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// Reset events
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r.events_stopped.reset();
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r.events_error.reset();
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r.events_lasttx.reset();
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self.clear_errorsrc();
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// Enable events
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r.intenset.write(|w| w.stopped().set().error().set());
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// Start write operation.
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r.shorts.write(|w| w.lasttx_stop().enabled());
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r.tasks_starttx.write(|w|
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// `1` is a valid value to write to task registers.
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unsafe { w.bits(1) });
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// after all possible DMA actions have completed.
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compiler_fence(SeqCst);
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// Wait for 'stopped' event.
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poll_fn(Self::wait_for_stopped_event).await;
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self.read_errorsrc()?;
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if r.txd.amount.read().bits() != bytes.len() as u32 {
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return Err(Error::Transmit);
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}
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Ok(())
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}
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}
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fn write_read<'a>(
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&'a mut self,
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address: u8,
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bytes: &'a [u8],
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buffer: &'a mut [u8],
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) -> Self::WriteReadFuture<'a> {
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async move {
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slice_in_ram_or(bytes, Error::DMABufferNotInDataMemory)?;
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// NOTE: RAM slice check for buffer is not necessary, as a mutable
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// slice can only be built from data located in RAM.
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// before any DMA action has started.
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compiler_fence(SeqCst);
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let r = T::regs();
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// Set up current address we're trying to talk to
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r.address.write(|w| unsafe { w.address().bits(address) });
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// Set up DMA buffers.
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unsafe {
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self.set_tx_buffer(bytes)?;
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self.set_rx_buffer(buffer)?;
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}
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// Reset events
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r.events_stopped.reset();
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r.events_error.reset();
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r.events_lasttx.reset();
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self.clear_errorsrc();
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// Enable events
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r.intenset.write(|w| w.stopped().set().error().set());
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// Start write+read operation.
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r.shorts.write(|w| {
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w.lasttx_startrx().enabled();
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w.lastrx_stop().enabled();
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w
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});
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// `1` is a valid value to write to task registers.
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r.tasks_starttx.write(|w| unsafe { w.bits(1) });
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// after all possible DMA actions have completed.
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compiler_fence(SeqCst);
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// Wait for 'stopped' event.
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poll_fn(Self::wait_for_stopped_event).await;
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self.read_errorsrc()?;
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let bad_write = r.txd.amount.read().bits() != bytes.len() as u32;
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let bad_read = r.rxd.amount.read().bits() != buffer.len() as u32;
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if bad_write {
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return Err(Error::Transmit);
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}
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if bad_read {
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return Err(Error::Receive);
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}
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Ok(())
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}
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}
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}
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impl<'a, T: Instance> embedded_hal::blocking::i2c::Write for Twim<'a, T> {
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type Error = Error;
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@ -94,9 +94,15 @@ pub trait I2c<A: AddressMode = SevenBitAddress> {
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/// Error type
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type Error;
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type ReadFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a;
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type WriteFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a;
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type WriteReadFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a;
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type WriteFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a
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where
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Self: 'a;
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type ReadFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a
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where
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Self: 'a;
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type WriteReadFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a
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where
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Self: 'a;
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/// Reads enough bytes from slave with `address` to fill `buffer`
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///
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@ -116,7 +122,7 @@ pub trait I2c<A: AddressMode = SevenBitAddress> {
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/// - `MAK` = master acknowledge
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/// - `NMAK` = master no acknowledge
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/// - `SP` = stop condition
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fn read<'a>(&'a mut self, address: A, buffer: &mut [u8]) -> Self::ReadFuture<'a>;
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fn read<'a>(&'a mut self, address: A, buffer: &'a mut [u8]) -> Self::ReadFuture<'a>;
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/// Sends bytes to slave with address `address`
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///
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@ -134,7 +140,7 @@ pub trait I2c<A: AddressMode = SevenBitAddress> {
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/// - `SAK` = slave acknowledge
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/// - `Bi` = ith byte of data
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/// - `SP` = stop condition
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fn write<'a>(&'a mut self, address: A, bytes: &[u8]) -> Self::WriteFuture<'a>;
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fn write<'a>(&'a mut self, address: A, bytes: &'a [u8]) -> Self::WriteFuture<'a>;
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/// Sends bytes to slave with address `address` and then reads enough bytes to fill `buffer` *in a
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/// single transaction*
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@ -161,7 +167,7 @@ pub trait I2c<A: AddressMode = SevenBitAddress> {
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fn write_read<'a>(
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&'a mut self,
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address: A,
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bytes: &[u8],
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buffer: &mut [u8],
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bytes: &'a [u8],
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buffer: &'a mut [u8],
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) -> Self::WriteReadFuture<'a>;
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}
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