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stm32/rcc: consistent casing and naming for PLL enums.

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This commit is contained in:
Dario Nieuwenhuis 2023-11-13 00:52:01 +01:00
parent 39c7371621
commit 4fe344ebc0
26 changed files with 111 additions and 111 deletions
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46
embassy-stm32/src/rcc/f2.rs
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@ -1,7 +1,7 @@
use crate::pac::flash::vals::Latency;
use crate::pac::rcc::vals::Sw;
pub use crate::pac::rcc::vals::{
Hpre as AHBPrescaler, Pllm as PLLPreDiv, Plln as PLLMul, Pllp as PLLPDiv, Pllq as PLLQDiv, Pllsrc as PLLSrc,
Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllsrc as PllSource,
Ppre as APBPrescaler,
};
use crate::pac::{FLASH, RCC};
@ -35,30 +35,30 @@ pub enum HSESrc {
}
#[derive(Clone, Copy)]
pub struct PLLConfig {
pub pre_div: PLLPreDiv,
pub mul: PLLMul,
pub p_div: PLLPDiv,
pub q_div: PLLQDiv,
pub struct Pll {
pub pre_div: PllPreDiv,
pub mul: PllMul,
pub divp: PllPDiv,
pub divq: PllQDiv,
}
impl Default for PLLConfig {
impl Default for Pll {
fn default() -> Self {
PLLConfig {
pre_div: PLLPreDiv::DIV16,
mul: PLLMul::MUL192,
p_div: PLLPDiv::DIV2,
q_div: PLLQDiv::DIV4,
Pll {
pre_div: PllPreDiv::DIV16,
mul: PllMul::MUL192,
divp: PllPDiv::DIV2,
divq: PllQDiv::DIV4,
}
}
}
impl PLLConfig {
impl Pll {
pub fn clocks(&self, src_freq: Hertz) -> PLLClocks {
let in_freq = src_freq / self.pre_div;
let vco_freq = src_freq / self.pre_div * self.mul;
let main_freq = vco_freq / self.p_div;
let pll48_freq = vco_freq / self.q_div;
let main_freq = vco_freq / self.divp;
let pll48_freq = vco_freq / self.divq;
PLLClocks {
in_freq,
vco_freq,
@ -172,8 +172,8 @@ impl VoltageScale {
pub struct Config {
pub hse: Option<HSEConfig>,
pub hsi: bool,
pub pll_mux: PLLSrc,
pub pll: PLLConfig,
pub pll_mux: PllSource,
pub pll: Pll,
pub mux: ClockSrc,
pub voltage: VoltageScale,
pub ahb_pre: AHBPrescaler,
@ -188,8 +188,8 @@ impl Default for Config {
Config {
hse: None,
hsi: true,
pll_mux: PLLSrc::HSI,
pll: PLLConfig::default(),
pll_mux: PllSource::HSI,
pll: Pll::default(),
voltage: VoltageScale::Range3,
mux: ClockSrc::HSI,
ahb_pre: AHBPrescaler::DIV1,
@ -217,13 +217,13 @@ pub(crate) unsafe fn init(config: Config) {
}
let pll_src_freq = match config.pll_mux {
PLLSrc::HSE => {
PllSource::HSE => {
let hse_config = config
.hse
.unwrap_or_else(|| panic!("HSE must be configured to be used as PLL input"));
hse_config.frequency
}
PLLSrc::HSI => HSI_FREQ,
PllSource::HSI => HSI_FREQ,
};
// Reference: STM32F215xx/217xx datasheet Table 33. Main PLL characteristics
@ -238,8 +238,8 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllsrc(config.pll_mux);
w.set_pllm(config.pll.pre_div);
w.set_plln(config.pll.mul);
w.set_pllp(config.pll.p_div);
w.set_pllq(config.pll.q_div);
w.set_pllp(config.pll.divp);
w.set_pllq(config.pll.divq);
});
let (sys_clk, sw) = match config.mux {

14
embassy-stm32/src/rcc/g0.rs
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@ -28,7 +28,7 @@ pub enum ClockSrc {
#[derive(Clone, Copy)]
pub struct PllConfig {
/// The source from which the PLL receives a clock signal
pub source: PllSrc,
pub source: PllSource,
/// The initial divisor of that clock signal
pub m: Pllm,
/// The PLL VCO multiplier, which must be in the range `8..=86`.
@ -48,7 +48,7 @@ impl Default for PllConfig {
fn default() -> PllConfig {
// HSI / 1 * 8 / 2 = 64 MHz
PllConfig {
source: PllSrc::HSI,
source: PllSource::HSI,
m: Pllm::DIV1,
n: Plln::MUL8,
r: Pllr::DIV2,
@ -59,7 +59,7 @@ impl Default for PllConfig {
}
#[derive(Clone, Copy, Eq, PartialEq)]
pub enum PllSrc {
pub enum PllSource {
HSI,
HSE(Hertz),
}
@ -89,8 +89,8 @@ impl Default for Config {
impl PllConfig {
pub(crate) fn init(self) -> Hertz {
let (src, input_freq) = match self.source {
PllSrc::HSI => (vals::Pllsrc::HSI, HSI_FREQ),
PllSrc::HSE(freq) => (vals::Pllsrc::HSE, freq),
PllSource::HSI => (vals::Pllsrc::HSI, HSI_FREQ),
PllSource::HSE(freq) => (vals::Pllsrc::HSE, freq),
};
let m_freq = input_freq / self.m;
@ -121,11 +121,11 @@ impl PllConfig {
// > 3. Change the desired parameter.
// Enable whichever clock source we're using, and wait for it to become ready
match self.source {
PllSrc::HSI => {
PllSource::HSI => {
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
}
PllSrc::HSE(_) => {
PllSource::HSE(_) => {
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
}

14
embassy-stm32/src/rcc/g4.rs
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@ -23,16 +23,16 @@ pub enum ClockSrc {
/// PLL clock input source
#[derive(Clone, Copy, Debug)]
pub enum PllSrc {
pub enum PllSource {
HSI,
HSE(Hertz),
}
impl Into<Pllsrc> for PllSrc {
impl Into<Pllsrc> for PllSource {
fn into(self) -> Pllsrc {
match self {
PllSrc::HSE(..) => Pllsrc::HSE,
PllSrc::HSI => Pllsrc::HSI,
PllSource::HSE(..) => Pllsrc::HSE,
PllSource::HSI => Pllsrc::HSI,
}
}
}
@ -44,7 +44,7 @@ impl Into<Pllsrc> for PllSrc {
/// frequency ranges for each of these settings.
pub struct Pll {
/// PLL Source clock selection.
pub source: PllSrc,
pub source: PllSource,
/// PLL pre-divider
pub prediv_m: PllM,
@ -118,13 +118,13 @@ pub struct PllFreq {
pub(crate) unsafe fn init(config: Config) {
let pll_freq = config.pll.map(|pll_config| {
let src_freq = match pll_config.source {
PllSrc::HSI => {
PllSource::HSI => {
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
HSI_FREQ
}
PllSrc::HSE(freq) => {
PllSource::HSE(freq) => {
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
freq

10
embassy-stm32/src/rcc/l0l1.rs
View File

@ -1,7 +1,7 @@
pub use crate::pac::pwr::vals::Vos as VoltageScale;
pub use crate::pac::rcc::vals::{
Hpre as AHBPrescaler, Msirange as MSIRange, Plldiv as PLLDiv, Plldiv as PllDiv, Pllmul as PLLMul, Pllmul as PllMul,
Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
Hpre as AHBPrescaler, Msirange as MSIRange, Plldiv as PllDiv, Pllmul as PllMul, Pllsrc as PllSource,
Ppre as APBPrescaler, Sw as ClockSrc,
};
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::{set_freqs, Clocks};
@ -29,7 +29,7 @@ pub struct Hse {
#[derive(Clone, Copy)]
pub struct Pll {
/// PLL source
pub source: PLLSource,
pub source: PllSource,
/// PLL multiplication factor.
pub mul: PllMul,
@ -116,8 +116,8 @@ pub(crate) unsafe fn init(config: Config) {
let pll = config.pll.map(|pll| {
let freq = match pll.source {
PLLSource::HSE => hse.unwrap(),
PLLSource::HSI => hsi.unwrap(),
PllSource::HSE => hse.unwrap(),
PllSource::HSI => hsi.unwrap(),
};
// Disable PLL

14
embassy-stm32/src/rcc/l4l5.rs
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@ -5,7 +5,7 @@ pub use crate::pac::rcc::vals::Clk48sel as Clk48Src;
pub use crate::pac::rcc::vals::Hsepre as HsePrescaler;
pub use crate::pac::rcc::vals::{
Adcsel as AdcClockSource, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul,
Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PllSource, Ppre as APBPrescaler, Sw as ClockSrc,
};
use crate::pac::{FLASH, RCC};
use crate::rcc::{set_freqs, Clocks};
@ -36,7 +36,7 @@ pub struct Hse {
#[derive(Clone, Copy)]
pub struct Pll {
/// PLL source
pub source: PLLSource,
pub source: PllSource,
/// PLL pre-divider (DIVM).
pub prediv: PllPreDiv,
@ -135,7 +135,7 @@ pub const WPAN_DEFAULT: Config = Config {
ls: super::LsConfig::default_lse(),
pll: Some(Pll {
source: PLLSource::HSE,
source: PllSource::HSE,
prediv: PllPreDiv::DIV2,
mul: PllMul::MUL12,
divp: Some(PllPDiv::DIV3), // 32 / 2 * 12 / 3 = 64Mhz
@ -456,10 +456,10 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
let Some(pll) = config else { return PllOutput::default() };
let pll_src = match pll.source {
PLLSource::DISABLE => panic!("must not select PLL source as DISABLE"),
PLLSource::HSE => input.hse,
PLLSource::HSI => input.hsi,
PLLSource::MSI => input.msi,
PllSource::DISABLE => panic!("must not select PLL source as DISABLE"),
PllSource::HSE => input.hse,
PllSource::HSI => input.hsi,
PllSource::MSI => input.msi,
};
let pll_src = pll_src.unwrap();

22
embassy-stm32/src/rcc/u5.rs
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@ -35,7 +35,7 @@ impl Default for ClockSrc {
#[derive(Clone, Copy)]
pub struct PllConfig {
/// The clock source for the PLL.
pub source: PllSrc,
pub source: PllSource,
/// The PLL prescaler.
///
/// The clock speed of the `source` divided by `m` must be between 4 and 16 MHz.
@ -57,7 +57,7 @@ impl PllConfig {
/// A configuration for HSI / 1 * 10 / 1 = 160 MHz
pub const fn hsi_160mhz() -> Self {
PllConfig {
source: PllSrc::HSI,
source: PllSource::HSI,
m: Pllm::DIV1,
n: Plln::MUL10,
r: Plldiv::DIV1,
@ -67,7 +67,7 @@ impl PllConfig {
/// A configuration for MSIS @ 48 MHz / 3 * 10 / 1 = 160 MHz
pub const fn msis_160mhz() -> Self {
PllConfig {
source: PllSrc::MSIS(Msirange::RANGE_48MHZ),
source: PllSource::MSIS(Msirange::RANGE_48MHZ),
m: Pllm::DIV3,
n: Plln::MUL10,
r: Plldiv::DIV1,
@ -76,7 +76,7 @@ impl PllConfig {
}
#[derive(Clone, Copy)]
pub enum PllSrc {
pub enum PllSource {
/// Use an internal medium speed oscillator as the PLL source.
MSIS(Msirange),
/// Use the external high speed clock as the system PLL source.
@ -88,12 +88,12 @@ pub enum PllSrc {
HSI,
}
impl Into<Pllsrc> for PllSrc {
impl Into<Pllsrc> for PllSource {
fn into(self) -> Pllsrc {
match self {
PllSrc::MSIS(..) => Pllsrc::MSIS,
PllSrc::HSE(..) => Pllsrc::HSE,
PllSrc::HSI => Pllsrc::HSI,
PllSource::MSIS(..) => Pllsrc::MSIS,
PllSource::HSE(..) => Pllsrc::HSE,
PllSource::HSI => Pllsrc::HSI,
}
}
}
@ -216,9 +216,9 @@ pub(crate) unsafe fn init(config: Config) {
ClockSrc::PLL1_R(pll) => {
// Configure the PLL source
let source_clk = match pll.source {
PllSrc::MSIS(range) => config.init_msis(range),
PllSrc::HSE(hertz) => config.init_hse(hertz),
PllSrc::HSI => config.init_hsi(),
PllSource::MSIS(range) => config.init_msis(range),
PllSource::HSE(hertz) => config.init_hse(hertz),
PllSource::HSI => config.init_hsi(),
};
// Calculate the reference clock, which is the source divided by m

8
embassy-stm32/src/rcc/wba.rs
View File

@ -17,16 +17,16 @@ pub enum ClockSrc {
}
#[derive(Clone, Copy, Debug)]
pub enum PllSrc {
pub enum PllSource {
HSE(Hertz),
HSI,
}
impl Into<Pllsrc> for PllSrc {
impl Into<Pllsrc> for PllSource {
fn into(self) -> Pllsrc {
match self {
PllSrc::HSE(..) => Pllsrc::HSE,
PllSrc::HSI => Pllsrc::HSI,
PllSource::HSE(..) => Pllsrc::HSE,
PllSource::HSI => Pllsrc::HSI,
}
}
}

14
examples/stm32f2/src/bin/pll.rs
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@ -7,7 +7,7 @@ use core::convert::TryFrom;
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::rcc::{
APBPrescaler, ClockSrc, HSEConfig, HSESrc, PLLConfig, PLLMul, PLLPDiv, PLLPreDiv, PLLQDiv, PLLSrc,
APBPrescaler, ClockSrc, HSEConfig, HSESrc, Pll, PllMul, PllPDiv, PllPreDiv, PllQDiv, PllSource,
};
use embassy_stm32::time::Hertz;
use embassy_stm32::Config;
@ -25,16 +25,16 @@ async fn main(_spawner: Spawner) {
source: HSESrc::Bypass,
});
// PLL uses HSE as the clock source
config.rcc.pll_mux = PLLSrc::HSE;
config.rcc.pll = PLLConfig {
config.rcc.pll_mux = PllSource::HSE;
config.rcc.pll = Pll {
// 8 MHz clock source / 8 = 1 MHz PLL input
pre_div: unwrap!(PLLPreDiv::try_from(8)),
pre_div: unwrap!(PllPreDiv::try_from(8)),
// 1 MHz PLL input * 240 = 240 MHz PLL VCO
mul: unwrap!(PLLMul::try_from(240)),
mul: unwrap!(PllMul::try_from(240)),
// 240 MHz PLL VCO / 2 = 120 MHz main PLL output
p_div: PLLPDiv::DIV2,
divp: PllPDiv::DIV2,
// 240 MHz PLL VCO / 5 = 48 MHz PLL48 output
q_div: PLLQDiv::DIV5,
divq: PllQDiv::DIV5,
};
// System clock comes from PLL (= the 120 MHz main PLL output)
config.rcc.mux = ClockSrc::PLL;

4
examples/stm32g4/src/bin/adc.rs
View File

@ -5,7 +5,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::adc::{Adc, SampleTime};
use embassy_stm32::rcc::{AdcClockSource, ClockSrc, Pll, PllM, PllN, PllR, PllSrc};
use embassy_stm32::rcc::{AdcClockSource, ClockSrc, Pll, PllM, PllN, PllR, PllSource};
use embassy_stm32::Config;
use embassy_time::{Delay, Timer};
use {defmt_rtt as _, panic_probe as _};
@ -15,7 +15,7 @@ async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.rcc.pll = Some(Pll {
source: PllSrc::HSI,
source: PllSource::HSI,
prediv_m: PllM::DIV4,
mul_n: PllN::MUL85,
div_p: None,

4
examples/stm32g4/src/bin/pll.rs
View File

@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::rcc::{ClockSrc, Pll, PllM, PllN, PllR, PllSrc};
use embassy_stm32::rcc::{ClockSrc, Pll, PllM, PllN, PllR, PllSource};
use embassy_stm32::Config;
use embassy_time::Timer;
use {defmt_rtt as _, panic_probe as _};
@ -14,7 +14,7 @@ async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.rcc.pll = Some(Pll {
source: PllSrc::HSI,
source: PllSource::HSI,
prediv_m: PllM::DIV4,
mul_n: PllN::MUL85,
div_p: None,

8
examples/stm32g4/src/bin/usb_serial.rs
View File

@ -4,7 +4,7 @@
use defmt::{panic, *};
use embassy_executor::Spawner;
use embassy_stm32::rcc::{Clock48MhzSrc, ClockSrc, Hsi48Config, Pll, PllM, PllN, PllQ, PllR, PllSrc};
use embassy_stm32::rcc::{Clock48MhzSrc, ClockSrc, Hsi48Config, Pll, PllM, PllN, PllQ, PllR, PllSource};
use embassy_stm32::time::Hertz;
use embassy_stm32::usb::{self, Driver, Instance};
use embassy_stm32::{bind_interrupts, peripherals, Config};
@ -25,14 +25,14 @@ async fn main(_spawner: Spawner) {
// Change this to `false` to use the HSE clock source for the USB. This example assumes an 8MHz HSE.
const USE_HSI48: bool = true;
let pllq_div = if USE_HSI48 { None } else { Some(PllQ::DIV6) };
let plldivq = if USE_HSI48 { None } else { Some(PllQ::DIV6) };
config.rcc.pll = Some(Pll {
source: PllSrc::HSE(Hertz(8_000_000)),
source: PllSource::HSE(Hertz(8_000_000)),
prediv_m: PllM::DIV2,
mul_n: PllN::MUL72,
div_p: None,
div_q: pllq_div,
div_q: plldivq,
// Main system clock at 144 MHz
div_r: Some(PllR::DIV2),
});

4
examples/stm32l4/src/bin/rng.rs
View File

@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::rcc::{ClockSrc, PLLSource, Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv};
use embassy_stm32::rcc::{ClockSrc, Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv, PllSource};
use embassy_stm32::rng::Rng;
use embassy_stm32::{bind_interrupts, peripherals, rng, Config};
use {defmt_rtt as _, panic_probe as _};
@ -19,7 +19,7 @@ async fn main(_spawner: Spawner) {
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.hsi = true;
config.rcc.pll = Some(Pll {
source: PLLSource::HSI,
source: PllSource::HSI,
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL18,
divp: None,

2
examples/stm32l4/src/bin/rtc.rs
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@ -22,7 +22,7 @@ async fn main(_spawner: Spawner) {
mode: HseMode::Oscillator,
});
config.rcc.pll = Some(Pll {
source: PLLSource::HSE,
source: PllSource::HSE,
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL20,
divp: None,

4
examples/stm32l4/src/bin/spe_adin1110_http_server.rs
View File

@ -75,7 +75,7 @@ async fn main(spawner: Spawner) {
let mut config = embassy_stm32::Config::default();
{
use embassy_stm32::rcc::*;
// 80Mhz clock (Source: 8 / SrcDiv: 1 * PLLMul 20 / ClkDiv 2)
// 80Mhz clock (Source: 8 / SrcDiv: 1 * PllMul 20 / ClkDiv 2)
// 80MHz highest frequency for flash 0 wait.
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.hse = Some(Hse {
@ -83,7 +83,7 @@ async fn main(spawner: Spawner) {
mode: HseMode::Oscillator,
});
config.rcc.pll = Some(Pll {
source: PLLSource::HSE,
source: PllSource::HSE,
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL20,
divp: None,

2
examples/stm32l4/src/bin/usb_serial.rs
View File

@ -27,7 +27,7 @@ async fn main(_spawner: Spawner) {
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.hsi = true;
config.rcc.pll = Some(Pll {
source: PLLSource::HSI,
source: PllSource::HSI,
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL10,
divp: None,

4
examples/stm32l5/src/bin/rng.rs
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@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::rcc::{ClockSrc, PLLSource, Pll, PllMul, PllPreDiv, PllRDiv};
use embassy_stm32::rcc::{ClockSrc, Pll, PllMul, PllPreDiv, PllRDiv, PllSource};
use embassy_stm32::rng::Rng;
use embassy_stm32::{bind_interrupts, peripherals, rng, Config};
use {defmt_rtt as _, panic_probe as _};
@ -20,7 +20,7 @@ async fn main(_spawner: Spawner) {
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.pll = Some(Pll {
// 64Mhz clock (16 / 1 * 8 / 2)
source: PLLSource::HSI,
source: PllSource::HSI,
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL8,
divp: None,

2
examples/stm32l5/src/bin/usb_ethernet.rs
View File

@ -49,7 +49,7 @@ async fn main(spawner: Spawner) {
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.pll = Some(Pll {
// 80Mhz clock (16 / 1 * 10 / 2)
source: PLLSource::HSI,
source: PllSource::HSI,
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL10,
divp: None,

2
examples/stm32l5/src/bin/usb_hid_mouse.rs
View File

@ -26,7 +26,7 @@ async fn main(_spawner: Spawner) {
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.pll = Some(Pll {
// 80Mhz clock (16 / 1 * 10 / 2)
source: PLLSource::HSI,
source: PllSource::HSI,
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL10,
divp: None,

2
examples/stm32l5/src/bin/usb_serial.rs
View File

@ -24,7 +24,7 @@ async fn main(_spawner: Spawner) {
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.pll = Some(Pll {
// 80Mhz clock (16 / 1 * 10 / 2)
source: PLLSource::HSI,
source: PllSource::HSI,
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL10,
divp: None,

2
examples/stm32u5/src/bin/usb_serial.rs
View File

@ -24,7 +24,7 @@ async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.rcc.mux = ClockSrc::PLL1_R(PllConfig {
source: PllSrc::HSI,
source: PllSource::HSI,
m: Pllm::DIV2,
n: Plln::MUL10,
r: Plldiv::DIV1,

2
examples/stm32wl/src/bin/lora_lorawan.rs
View File

@ -44,7 +44,7 @@ async fn main(_spawner: Spawner) {
});
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.pll = Some(Pll {
source: PLLSource::HSE,
source: PllSource::HSE,
prediv: PllPreDiv::DIV2,
mul: PllMul::MUL6,
divp: None,

2
examples/stm32wl/src/bin/lora_p2p_receive.rs
View File

@ -37,7 +37,7 @@ async fn main(_spawner: Spawner) {
});
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.pll = Some(Pll {
source: PLLSource::HSE,
source: PllSource::HSE,
prediv: PllPreDiv::DIV2,
mul: PllMul::MUL6,
divp: None,

2
examples/stm32wl/src/bin/lora_p2p_send.rs
View File

@ -37,7 +37,7 @@ async fn main(_spawner: Spawner) {
});
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.pll = Some(Pll {
source: PLLSource::HSE,
source: PllSource::HSE,
prediv: PllPreDiv::DIV2,
mul: PllMul::MUL6,
divp: None,

2
examples/stm32wl/src/bin/random.rs
View File

@ -25,7 +25,7 @@ async fn main(_spawner: Spawner) {
});
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.pll = Some(Pll {
source: PLLSource::HSE,
source: PllSource::HSE,
prediv: PllPreDiv::DIV2,
mul: PllMul::MUL6,
divp: None,

2
examples/stm32wl/src/bin/rtc.rs
View File

@ -24,7 +24,7 @@ async fn main(_spawner: Spawner) {
});
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.pll = Some(Pll {
source: PLLSource::HSE,
source: PllSource::HSE,
prediv: PllPreDiv::DIV2,
mul: PllMul::MUL6,
divp: None,

30
tests/stm32/src/common.rs
View File

@ -241,16 +241,16 @@ pub fn config() -> Config {
source: HSESrc::Bypass,
});
// PLL uses HSE as the clock source
config.rcc.pll_mux = PLLSrc::HSE;
config.rcc.pll = PLLConfig {
config.rcc.pll_mux = PllSource::HSE;
config.rcc.pll = Pll {
// 8 MHz clock source / 8 = 1 MHz PLL input
pre_div: unwrap!(PLLPreDiv::try_from(8)),
pre_div: unwrap!(PllPreDiv::try_from(8)),
// 1 MHz PLL input * 240 = 240 MHz PLL VCO
mul: unwrap!(PLLMul::try_from(240)),
mul: unwrap!(PllMul::try_from(240)),
// 240 MHz PLL VCO / 2 = 120 MHz main PLL output
p_div: PLLPDiv::DIV2,
divp: PllPDiv::DIV2,
// 240 MHz PLL VCO / 5 = 48 MHz PLL48 output
q_div: PLLQDiv::DIV5,
divq: PllQDiv::DIV5,
};
// System clock comes from PLL (= the 120 MHz main PLL output)
config.rcc.mux = ClockSrc::PLL;
@ -397,7 +397,7 @@ pub fn config() -> Config {
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.hsi = true;
config.rcc.pll = Some(Pll {
source: PLLSource::HSI,
source: PllSource::HSI,
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL18,
divp: None,
@ -416,7 +416,7 @@ pub fn config() -> Config {
});
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.pll = Some(Pll {
source: PLLSource::HSE,
source: PllSource::HSE,
prediv: PllPreDiv::DIV2,
mul: PllMul::MUL6,
divp: None,
@ -432,7 +432,7 @@ pub fn config() -> Config {
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.pll = Some(Pll {
// 110Mhz clock (16 / 4 * 55 / 2)
source: PLLSource::HSI,
source: PllSource::HSI,
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL55,
divp: None,
@ -462,9 +462,9 @@ pub fn config() -> Config {
use embassy_stm32::rcc::*;
config.rcc.hsi = true;
config.rcc.pll = Some(Pll {
source: PLLSource::HSI,
mul: PLLMul::MUL4,
div: PLLDiv::DIV2, // 32Mhz clock (16 * 4 / 2)
source: PllSource::HSI,
mul: PllMul::MUL4,
div: PllDiv::DIV2, // 32Mhz clock (16 * 4 / 2)
});
config.rcc.mux = ClockSrc::PLL1_P;
}
@ -474,9 +474,9 @@ pub fn config() -> Config {
use embassy_stm32::rcc::*;
config.rcc.hsi = true;
config.rcc.pll = Some(Pll {
source: PLLSource::HSI,
mul: PLLMul::MUL4,
div: PLLDiv::DIV2, // 32Mhz clock (16 * 4 / 2)
source: PllSource::HSI,
mul: PllMul::MUL4,
div: PllDiv::DIV2, // 32Mhz clock (16 * 4 / 2)
});
config.rcc.mux = ClockSrc::PLL1_P;
}