diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs
index bb95af966..2d9c63820 100644
--- a/embassy-stm32/src/usart/ringbuffered.rs
+++ b/embassy-stm32/src/usart/ringbuffered.rs
@@ -71,33 +71,18 @@ impl<'d> UartRx<'d, Async> {
 }
 
 impl<'d> RingBufferedUartRx<'d> {
-    /// Clear the ring buffer and start receiving in the background
-    pub fn start(&mut self) -> Result<(), Error> {
-        // Clear the ring buffer so that it is ready to receive data
-        self.ring_buf.clear();
-
-        self.setup_uart();
-
-        Ok(())
-    }
-
-    fn stop(&mut self, err: Error) -> Result<usize, Error> {
-        self.teardown_uart();
-
-        Err(err)
-    }
-
     /// Reconfigure the driver
     pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
         reconfigure(self.info, self.kernel_clock, config)
     }
 
-    /// Start uart background receive
-    fn setup_uart(&mut self) {
-        // fence before starting DMA.
+    /// Configure and start the DMA backed UART receiver
+    ///
+    /// Note: This is also done automatically by [`read()`] if required.
+    pub fn start_uart(&mut self) {
+        // Clear the buffer so that it is ready to receive data
+        self.ring_buf.clear();
         compiler_fence(Ordering::SeqCst);
-
-        // start the dma controller
         self.ring_buf.start();
 
         let r = self.info.regs;
@@ -118,8 +103,8 @@ impl<'d> RingBufferedUartRx<'d> {
         });
     }
 
-    /// Stop uart background receive
-    fn teardown_uart(&mut self) {
+    /// Stop DMA backed UART receiver
+    fn stop_uart(&mut self) {
         self.ring_buf.request_pause();
 
         let r = self.info.regs;
@@ -153,13 +138,15 @@ impl<'d> RingBufferedUartRx<'d> {
     pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
         let r = self.info.regs;
 
-        // Start background receive if it was not already started
+        // Start DMA and Uart if it was not already started,
+        // otherwise check for errors in status register.
+        let sr = clear_idle_flag(r);
         if !r.cr3().read().dmar() {
-            self.start()?;
+            self.start_uart();
+        } else {
+            check_for_errors(sr)?;
         }
 
-        check_for_errors(clear_idle_flag(r))?;
-
         loop {
             match self.ring_buf.read(buf) {
                 Ok((0, _)) => {}
@@ -167,14 +154,16 @@ impl<'d> RingBufferedUartRx<'d> {
                     return Ok(len);
                 }
                 Err(_) => {
-                    return self.stop(Error::Overrun);
+                    self.stop_uart();
+                    return Err(Error::Overrun);
                 }
             }
 
             match self.wait_for_data_or_idle().await {
                 Ok(_) => {}
                 Err(err) => {
-                    return self.stop(err);
+                    self.stop_uart();
+                    return Err(err);
                 }
             }
         }
@@ -228,7 +217,7 @@ impl<'d> RingBufferedUartRx<'d> {
 
 impl Drop for RingBufferedUartRx<'_> {
     fn drop(&mut self) {
-        self.teardown_uart();
+        self.stop_uart();
         self.rx.as_ref().map(|x| x.set_as_disconnected());
         self.rts.as_ref().map(|x| x.set_as_disconnected());
         super::drop_tx_rx(self.info, self.state);