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Merge pull request #2395 from swanandx/nrf-tx-nosck

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add new_tx_nosck for nrf
This commit is contained in:
Dario Nieuwenhuis 2024-01-03 16:50:58 +00:00 committed by GitHub
commit 4f3e1fa738
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 59 additions and 14 deletions
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31
embassy-nrf/src/spim.rs
View File

@ -99,7 +99,7 @@ impl<'d, T: Instance> Spim<'d, T> {
into_ref!(sck, miso, mosi);
Self::new_inner(
spim,
sck.map_into(),
Some(sck.map_into()),
Some(miso.map_into()),
Some(mosi.map_into()),
config,
@ -115,7 +115,7 @@ impl<'d, T: Instance> Spim<'d, T> {
config: Config,
) -> Self {
into_ref!(sck, mosi);
Self::new_inner(spim, sck.map_into(), None, Some(mosi.map_into()), config)
Self::new_inner(spim, Some(sck.map_into()), None, Some(mosi.map_into()), config)
}
/// Create a new SPIM driver, capable of RX only (MISO only).
@ -127,12 +127,23 @@ impl<'d, T: Instance> Spim<'d, T> {
config: Config,
) -> Self {
into_ref!(sck, miso);
Self::new_inner(spim, sck.map_into(), Some(miso.map_into()), None, config)
Self::new_inner(spim, Some(sck.map_into()), Some(miso.map_into()), None, config)
}
/// Create a new SPIM driver, capable of TX only (MOSI only), without SCK pin.
pub fn new_txonly_nosck(
spim: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
mosi: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Self {
into_ref!(mosi);
Self::new_inner(spim, None, None, Some(mosi.map_into()), config)
}
fn new_inner(
spim: impl Peripheral<P = T> + 'd,
sck: PeripheralRef<'d, AnyPin>,
sck: Option<PeripheralRef<'d, AnyPin>>,
miso: Option<PeripheralRef<'d, AnyPin>>,
mosi: Option<PeripheralRef<'d, AnyPin>>,
config: Config,
@ -142,7 +153,9 @@ impl<'d, T: Instance> Spim<'d, T> {
let r = T::regs();
// Configure pins
sck.conf().write(|w| w.dir().output().drive().h0h1());
if let Some(sck) = &sck {
sck.conf().write(|w| w.dir().output().drive().h0h1());
}
if let Some(mosi) = &mosi {
mosi.conf().write(|w| w.dir().output().drive().h0h1());
}
@ -152,13 +165,17 @@ impl<'d, T: Instance> Spim<'d, T> {
match config.mode.polarity {
Polarity::IdleHigh => {
sck.set_high();
if let Some(sck) = &sck {
sck.set_high();
}
if let Some(mosi) = &mosi {
mosi.set_high();
}
}
Polarity::IdleLow => {
sck.set_low();
if let Some(sck) = &sck {
sck.set_low();
}
if let Some(mosi) = &mosi {
mosi.set_low();
}

42
embassy-nrf/src/spis.rs
View File

@ -105,7 +105,7 @@ impl<'d, T: Instance> Spis<'d, T> {
Self::new_inner(
spis,
cs.map_into(),
sck.map_into(),
Some(sck.map_into()),
Some(miso.map_into()),
Some(mosi.map_into()),
config,
@ -122,7 +122,14 @@ impl<'d, T: Instance> Spis<'d, T> {
config: Config,
) -> Self {
into_ref!(cs, sck, miso);
Self::new_inner(spis, cs.map_into(), sck.map_into(), Some(miso.map_into()), None, config)
Self::new_inner(
spis,
cs.map_into(),
Some(sck.map_into()),
Some(miso.map_into()),
None,
config,
)
}
/// Create a new SPIS driver, capable of RX only (MOSI only).
@ -135,28 +142,49 @@ impl<'d, T: Instance> Spis<'d, T> {
config: Config,
) -> Self {
into_ref!(cs, sck, mosi);
Self::new_inner(spis, cs.map_into(), sck.map_into(), None, Some(mosi.map_into()), config)
Self::new_inner(
spis,
cs.map_into(),
Some(sck.map_into()),
None,
Some(mosi.map_into()),
config,
)
}
/// Create a new SPIS driver, capable of TX only (MISO only) without SCK pin.
pub fn new_txonly_nosck(
spis: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
cs: impl Peripheral<P = impl GpioPin> + 'd,
miso: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Self {
into_ref!(cs, miso);
Self::new_inner(spis, cs.map_into(), None, Some(miso.map_into()), None, config)
}
fn new_inner(
spis: impl Peripheral<P = T> + 'd,
cs: PeripheralRef<'d, AnyPin>,
sck: PeripheralRef<'d, AnyPin>,
sck: Option<PeripheralRef<'d, AnyPin>>,
miso: Option<PeripheralRef<'d, AnyPin>>,
mosi: Option<PeripheralRef<'d, AnyPin>>,
config: Config,
) -> Self {
compiler_fence(Ordering::SeqCst);
into_ref!(spis, cs, sck);
into_ref!(spis, cs);
let r = T::regs();
// Configure pins.
sck.conf().write(|w| w.input().connect().drive().h0h1());
r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) });
cs.conf().write(|w| w.input().connect().drive().h0h1());
r.psel.csn.write(|w| unsafe { w.bits(cs.psel_bits()) });
if let Some(sck) = &sck {
sck.conf().write(|w| w.input().connect().drive().h0h1());
r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) });
}
if let Some(mosi) = &mosi {
mosi.conf().write(|w| w.input().connect().drive().h0h1());
r.psel.mosi.write(|w| unsafe { w.bits(mosi.psel_bits()) });