mirror of
https://github.com/embassy-rs/embassy.git
synced 2024-11-22 23:02:30 +00:00
stm32/spi: add v4/v5 support (for H5).
This commit is contained in:
Dario Nieuwenhuis
parent
44b7fe45e2
commit
4ef8e008e8
@ -258,7 +258,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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w.set_spe(true);
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});
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}
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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unsafe {
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T::REGS.ifcr().write(|w| w.0 = 0xffff_ffff);
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T::REGS.cfg2().modify(|w| {
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@ -317,7 +317,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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});
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}
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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unsafe {
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T::REGS.cfg2().modify(|w| {
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w.set_cpha(cpha);
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@ -330,7 +330,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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pub fn get_current_config(&self) -> Config {
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#[cfg(any(spi_v1, spi_f1, spi_v2))]
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let cfg = unsafe { T::REGS.cr1().read() };
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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let cfg = unsafe { T::REGS.cfg2().read() };
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let polarity = if cfg.cpol() == vals::Cpol::IDLELOW {
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Polarity::IdleLow
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@ -383,7 +383,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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w.set_spe(true);
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});
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}
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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unsafe {
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T::REGS.cr1().modify(|w| {
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w.set_csusp(true);
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@ -429,7 +429,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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T::REGS.cr1().modify(|w| {
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w.set_spe(true);
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});
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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T::REGS.cr1().modify(|w| {
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w.set_cstart(true);
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});
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@ -459,7 +459,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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}
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// SPIv3 clears rxfifo on SPE=0
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#[cfg(not(any(spi_v3, spi_v4)))]
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#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
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flush_rx_fifo(T::REGS);
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set_rxdmaen(T::REGS, true);
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@ -481,7 +481,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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T::REGS.cr1().modify(|w| {
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w.set_spe(true);
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});
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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T::REGS.cr1().modify(|w| {
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w.set_cstart(true);
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});
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@ -514,7 +514,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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}
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// SPIv3 clears rxfifo on SPE=0
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#[cfg(not(any(spi_v3, spi_v4)))]
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#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
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flush_rx_fifo(T::REGS);
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set_rxdmaen(T::REGS, true);
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@ -534,7 +534,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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T::REGS.cr1().modify(|w| {
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w.set_spe(true);
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});
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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T::REGS.cr1().modify(|w| {
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w.set_cstart(true);
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});
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@ -619,9 +619,9 @@ impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
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}
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}
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#[cfg(not(any(spi_v3, spi_v4)))]
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#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
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use vals::Br;
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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use vals::Mbr as Br;
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fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> Br {
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@ -647,17 +647,17 @@ trait RegsExt {
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impl RegsExt for Regs {
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fn tx_ptr<W>(&self) -> *mut W {
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#[cfg(not(any(spi_v3, spi_v4)))]
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#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
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let dr = self.dr();
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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let dr = self.txdr();
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dr.ptr() as *mut W
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}
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fn rx_ptr<W>(&self) -> *mut W {
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#[cfg(not(any(spi_v3, spi_v4)))]
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#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
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let dr = self.dr();
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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let dr = self.rxdr();
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dr.ptr() as *mut W
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}
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@ -667,22 +667,22 @@ fn check_error_flags(sr: regs::Sr) -> Result<(), Error> {
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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#[cfg(not(any(spi_f1, spi_v3, spi_v4)))]
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#[cfg(not(any(spi_f1, spi_v3, spi_v4, spi_v5)))]
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if sr.fre() {
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return Err(Error::Framing);
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}
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.modf() {
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return Err(Error::ModeFault);
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}
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#[cfg(not(any(spi_v3, spi_v4)))]
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#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
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if sr.crcerr() {
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return Err(Error::Crc);
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}
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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if sr.crce() {
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return Err(Error::Crc);
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}
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@ -696,11 +696,11 @@ fn spin_until_tx_ready(regs: Regs) -> Result<(), Error> {
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check_error_flags(sr)?;
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#[cfg(not(any(spi_v3, spi_v4)))]
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#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
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if sr.txe() {
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return Ok(());
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}
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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if sr.txp() {
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return Ok(());
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}
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@ -713,11 +713,11 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
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check_error_flags(sr)?;
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#[cfg(not(any(spi_v3, spi_v4)))]
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#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
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if sr.rxne() {
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return Ok(());
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}
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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if sr.rxp() {
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return Ok(());
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}
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@ -726,11 +726,11 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
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fn flush_rx_fifo(regs: Regs) {
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unsafe {
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#[cfg(not(any(spi_v3, spi_v4)))]
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#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
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while regs.sr().read().rxne() {
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let _ = regs.dr().read();
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}
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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while regs.sr().read().rxp() {
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let _ = regs.rxdr().read();
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}
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@ -739,11 +739,11 @@ fn flush_rx_fifo(regs: Regs) {
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fn set_txdmaen(regs: Regs, val: bool) {
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unsafe {
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#[cfg(not(any(spi_v3, spi_v4)))]
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#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
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regs.cr2().modify(|reg| {
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reg.set_txdmaen(val);
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});
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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regs.cfg1().modify(|reg| {
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reg.set_txdmaen(val);
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});
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@ -752,11 +752,11 @@ fn set_txdmaen(regs: Regs, val: bool) {
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fn set_rxdmaen(regs: Regs, val: bool) {
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unsafe {
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#[cfg(not(any(spi_v3, spi_v4)))]
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#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
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regs.cr2().modify(|reg| {
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reg.set_rxdmaen(val);
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});
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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regs.cfg1().modify(|reg| {
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reg.set_rxdmaen(val);
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});
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@ -768,9 +768,9 @@ fn finish_dma(regs: Regs) {
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#[cfg(spi_v2)]
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while regs.sr().read().ftlvl() > 0 {}
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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while !regs.sr().read().txc() {}
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#[cfg(not(any(spi_v3, spi_v4)))]
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#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
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while regs.sr().read().bsy() {}
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// Disable the spi peripheral
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@ -780,12 +780,12 @@ fn finish_dma(regs: Regs) {
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// The peripheral automatically disables the DMA stream on completion without error,
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// but it does not clear the RXDMAEN/TXDMAEN flag in CR2.
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#[cfg(not(any(spi_v3, spi_v4)))]
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#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
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regs.cr2().modify(|reg| {
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reg.set_txdmaen(false);
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reg.set_rxdmaen(false);
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});
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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regs.cfg1().modify(|reg| {
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reg.set_txdmaen(false);
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reg.set_rxdmaen(false);
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@ -799,7 +799,7 @@ fn transfer_word<W: Word>(regs: Regs, tx_word: W) -> Result<W, Error> {
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unsafe {
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ptr::write_volatile(regs.tx_ptr(), tx_word);
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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regs.cr1().modify(|reg| reg.set_cstart(true));
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}
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@ -970,7 +970,7 @@ pub(crate) mod sealed {
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}
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}
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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pub fn dsize(&self) -> u8 {
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match self {
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WordSize::EightBit => 0b0111,
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@ -978,7 +978,7 @@ pub(crate) mod sealed {
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}
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}
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#[cfg(any(spi_v3, spi_v4))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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pub fn _frxth(&self) -> vals::Fthlv {
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match self {
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WordSize::EightBit => vals::Fthlv::ONEFRAME,
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