mirror of
https://github.com/embassy-rs/embassy.git
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stm32/rtc: build more chips
This commit is contained in:
xoviat
parent
f589247c1f
commit
4de4039417
@ -49,7 +49,7 @@ pub mod pwm;
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pub mod qspi;
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#[cfg(rng)]
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pub mod rng;
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#[cfg(all(rtc, not(any(rtc_v1, rtc_v2f0, rtc_v2f7, rtc_v3, rtc_v3u5))))]
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#[cfg(all(rtc, not(rtc_v1)))]
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pub mod rtc;
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#[cfg(sdmmc)]
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pub mod sdmmc;
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@ -9,7 +9,70 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
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pub(super) fn apply_config(&mut self, rtc_config: RtcConfig) {
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// Unlock the backup domain
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unsafe {
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unlock_backup_domain(rtc_config.clock_config as u8);
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let clock_config = rtc_config.clock_config as u8;
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#[cfg(not(rtc_v2wb))]
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use stm32_metapac::rcc::vals::Rtcsel;
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#[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))]
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let cr = crate::pac::PWR.cr();
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#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
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let cr = crate::pac::PWR.cr1();
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// TODO: Missing from PAC for l0 and f0?
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#[cfg(not(any(rtc_v2f0, rtc_v2l0)))]
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{
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cr.modify(|w| w.set_dbp(true));
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while !cr.read().dbp() {}
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}
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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let reg = crate::pac::RCC.bdcr().read();
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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let reg = crate::pac::RCC.csr().read();
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#[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb))]
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assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
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#[cfg(rtc_v2wb)]
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let rtcsel = reg.rtcsel();
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#[cfg(not(rtc_v2wb))]
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let rtcsel = reg.rtcsel().0;
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if !reg.rtcen() || rtcsel != clock_config {
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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let cr = crate::pac::RCC.bdcr();
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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let cr = crate::pac::RCC.csr();
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cr.modify(|w| {
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// Reset
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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w.set_bdrst(false);
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// Select RTC source
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#[cfg(not(rtc_v2wb))]
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w.set_rtcsel(Rtcsel(clock_config));
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#[cfg(rtc_v2wb)]
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w.set_rtcsel(clock_config);
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w.set_rtcen(true);
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// Restore bcdr
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#[cfg(any(rtc_v2l4, rtc_v2wb))]
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w.set_lscosel(reg.lscosel());
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#[cfg(any(rtc_v2l4, rtc_v2wb))]
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w.set_lscoen(reg.lscoen());
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w.set_lseon(reg.lseon());
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#[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
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w.set_lsedrv(reg.lsedrv());
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w.set_lsebyp(reg.lsebyp());
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});
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}
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}
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self.write(true, |rtc| unsafe {
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@ -157,7 +220,7 @@ pub fn write_backup_register(rtc: &Rtc, register: usize, value: u32) {
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}
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pub(crate) unsafe fn enable_peripheral_clk() {
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#[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2l4, rtc_v2wb))]
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#[cfg(any(rtc_v2l4, rtc_v2wb))]
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{
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// enable peripheral clock for communication
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crate::pac::RCC.apb1enr1().modify(|w| w.set_rtcapben(true));
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@ -168,68 +231,3 @@ pub(crate) unsafe fn enable_peripheral_clk() {
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}
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pub const BACKUP_REGISTER_COUNT: usize = 20;
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pub(super) unsafe fn unlock_backup_domain(clock_config: u8) {
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#[cfg(not(rtc_v2wb))]
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use stm32_metapac::rcc::vals::Rtcsel;
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#[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))]
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let cr = crate::pac::PWR.cr();
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#[cfg(any(rtc_v2f0, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
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let cr = crate::pac::PWR.cr1();
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// TODO: Missing from PAC for l0?
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#[cfg(not(rtc_v2l0))]
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{
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cr.modify(|w| w.set_dbp(true));
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while !cr.read().dbp() {}
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}
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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let reg = crate::pac::RCC.bdcr().read();
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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let reg = crate::pac::RCC.csr().read();
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#[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
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assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
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#[cfg(rtc_v2wb)]
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let rtcsel = reg.rtcsel();
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#[cfg(not(rtc_v2wb))]
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let rtcsel = reg.rtcsel().0;
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if !reg.rtcen() || rtcsel != clock_config {
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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let cr = crate::pac::RCC.bdcr();
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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let cr = crate::pac::RCC.csr();
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cr.modify(|w| {
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// Reset
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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w.set_bdrst(false);
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// Select RTC source
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#[cfg(not(rtc_v2wb))]
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w.set_rtcsel(Rtcsel(clock_config));
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#[cfg(rtc_v2wb)]
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w.set_rtcsel(clock_config);
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w.set_rtcen(true);
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// Restore bcdr
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#[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2l4, rtc_v2wb))]
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w.set_lscosel(reg.lscosel());
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#[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2l4, rtc_v2wb))]
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w.set_lscoen(reg.lscoen());
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w.set_lseon(reg.lseon());
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#[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
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w.set_lsedrv(reg.lsedrv());
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w.set_lsebyp(reg.lsebyp());
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});
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}
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}
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@ -9,43 +9,30 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
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pub(super) fn apply_config(&mut self, rtc_config: RtcConfig) {
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// Unlock the backup domain
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unsafe {
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#[cfg(feature = "stm32g0c1ve")]
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#[cfg(any(rtc_v3u5, rcc_g0))]
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use crate::pac::rcc::vals::Rtcsel;
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#[cfg(not(any(rtc_v3u5, rcc_g0, rcc_g4, rcc_wl5, rcc_wle)))]
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use crate::pac::rtc::vals::Rtcsel;
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#[cfg(not(any(rtc_v3u5, rcc_wl5, rcc_wle)))]
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{
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crate::pac::PWR.cr1().modify(|w| w.set_dbp(true));
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while !crate::pac::PWR.cr1().read().dbp() {}
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}
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#[cfg(not(any(
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feature = "stm32g0c1ve",
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feature = "stm32g491re",
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feature = "stm32u585zi",
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feature = "stm32g473cc"
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)))]
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#[cfg(any(rcc_wl5, rcc_wle))]
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{
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crate::pac::PWR
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.cr1()
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.modify(|w| w.set_dbp(stm32_metapac::pwr::vals::Dbp::ENABLED));
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while crate::pac::PWR.cr1().read().dbp() != stm32_metapac::pwr::vals::Dbp::DISABLED {}
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use crate::pac::pwr::vals::Dbp;
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crate::pac::PWR.cr1().modify(|w| w.set_dbp(Dbp::ENABLED));
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while crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED {}
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}
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let reg = crate::pac::RCC.bdcr().read();
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assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
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let config_rtcsel = rtc_config.clock_config as u8;
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#[cfg(not(any(
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feature = "stm32wl54jc-cm0p",
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feature = "stm32wle5ub",
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feature = "stm32g0c1ve",
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feature = "stm32wl55jc-cm4",
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feature = "stm32wl55uc-cm4",
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feature = "stm32g491re",
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feature = "stm32g473cc",
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feature = "stm32u585zi",
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feature = "stm32wle5jb"
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)))]
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let config_rtcsel = stm32_metapac::rtc::vals::Rtcsel(config_rtcsel);
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#[cfg(feature = "stm32g0c1ve")]
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let config_rtcsel = stm32_metapac::rcc::vals::Rtcsel(config_rtcsel);
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#[cfg(not(any(rcc_wl5, rcc_wle, rcc_g4)))]
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let config_rtcsel = Rtcsel(config_rtcsel);
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if !reg.rtcen() || reg.rtcsel() != config_rtcsel {
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crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
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