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add spi_v4 and spi_v5 support but block i2scfg rx-only configuration
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@ -508,7 +508,7 @@ impl<'d> Spi<'d, Async> {
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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miso: impl Peripheral<P = impl MisoPin<T>> + 'd,
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#[cfg(any(spi_v1, spi_f1, spi_v4, spi_v5))] tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
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#[cfg(any(spi_v1, spi_f1, spi_v2))] tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
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rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
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config: Config,
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) -> Self {
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@ -517,9 +517,9 @@ impl<'d> Spi<'d, Async> {
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new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()),
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None,
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new_pin!(miso, AFType::Input, Speed::VeryHigh),
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#[cfg(any(spi_v1, spi_f1, spi_v4, spi_v5))]
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#[cfg(any(spi_v1, spi_f1, spi_v2))]
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new_dma!(tx_dma),
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#[cfg(any(spi_v2, spi_v3))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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None,
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new_dma!(rx_dma),
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config,
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@ -626,7 +626,7 @@ impl<'d> Spi<'d, Async> {
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}
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/// SPI read, using DMA.
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#[cfg(any(spi_v2, spi_v3))]
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
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if data.is_empty() {
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return Ok(());
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@ -644,6 +644,7 @@ impl<'d> Spi<'d, Async> {
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prev
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});
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#[cfg(spi_v3)]
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let i2scfg = regs.i2scfgr().modify(|w| {
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w.i2smod().then(|| {
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let prev = w.i2scfg();
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@ -713,6 +714,7 @@ impl<'d> Spi<'d, Async> {
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w.set_tsize(tsize);
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});
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#[cfg(spi_v3)]
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if let Some(i2scfg) = i2scfg {
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regs.i2scfgr().modify(|w| {
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w.set_i2scfg(i2scfg);
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@ -723,7 +725,7 @@ impl<'d> Spi<'d, Async> {
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}
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/// SPI read, using DMA.
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#[cfg(any(spi_v1, spi_f1, spi_v4, spi_v5))]
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#[cfg(any(spi_v1, spi_f1, spi_v2))]
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pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
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if data.is_empty() {
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return Ok(());
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