eth-v2: Start Ethernet peripheral implementation

embassy-net/src/lib.rs

@@ -13,7 +13,7 @@ pub use config::DhcpConfigurator;
 pub use config::{Config, Configurator, Event as ConfigEvent, StaticConfigurator};
 
 pub use device::{Device, LinkState};
-pub use packet_pool::{Packet, PacketBox, PacketBoxExt, PacketBuf};
+pub use packet_pool::{Packet, PacketBox, PacketBoxExt, PacketBuf, MTU};
 pub use stack::{init, is_config_up, is_init, is_link_up, run};
 
 #[cfg(feature = "tcp")]

embassy-net/src/packet_pool.rs

@@ -3,12 +3,13 @@ use core::ops::{Deref, DerefMut, Range};
 
 use atomic_pool::{pool, Box};
 
-pub const MTU: usize = 1514;
+pub const MTU: usize = 1516;
 pub const PACKET_POOL_SIZE: usize = 4;
 
 pool!(pub PacketPool: [Packet; PACKET_POOL_SIZE]);
 pub type PacketBox = Box<PacketPool>;
 
+#[repr(align(4))]
 pub struct Packet(pub [u8; MTU]);
 
 impl Packet {

embassy-stm32/Cargo.toml

@@ -10,6 +10,7 @@ embassy = { version = "0.1.0", path = "../embassy" }
 embassy-macros = { version = "0.1.0", path = "../embassy-macros", features = ["stm32"] }
 embassy-extras = {version = "0.1.0", path = "../embassy-extras" }
 embassy-traits = {version = "0.1.0", path = "../embassy-traits" }
+embassy-net = { version = "0.1.0", path = "../embassy-net", features = ["tcp", "medium-ip"] }
 
 defmt = { version = "0.2.0", optional = true }
 log = { version = "0.4.11", optional = true }
@@ -24,6 +25,8 @@ critical-section = "0.2.1"
 bare-metal = "1.0.0"
 atomic-polyfill = "0.1.2"
 stm32-metapac = { version = "0.1.0", path = "../stm32-metapac", features = ["rt"] }
+vcell = "0.1.3"
+
 cfg-if = "1.0.0"
 
 [build-dependencies]

embassy-stm32/src/eth/mod.rs

@@ -0,0 +1,7 @@
+#![macro_use]
+
+#[cfg_attr(eth_v1, path = "v1.rs")]
+#[cfg_attr(eth_v2, path = "v2/mod.rs")]
+mod _version;
+
+pub use _version::*;

embassy-stm32/src/eth/v1.rs

@@ -0,0 +1 @@
+

embassy-stm32/src/eth/v2/descriptors.rs

@@ -0,0 +1,371 @@
+use core::sync::atomic::{fence, Ordering};
+
+use embassy_net::{Packet, PacketBox, PacketBoxExt, PacketBuf};
+use vcell::VolatileCell;
+
+use crate::pac::ETH;
+
+#[non_exhaustive]
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Error {
+    NoBufferAvailable,
+    // TODO: Break down this error into several others
+    TransmissionError,
+}
+
+/// Transmit and Receive Descriptor fields
+#[allow(dead_code)]
+mod emac_consts {
+    pub const EMAC_DES3_OWN: u32 = 0x8000_0000;
+    pub const EMAC_DES3_CTXT: u32 = 0x4000_0000;
+    pub const EMAC_DES3_FD: u32 = 0x2000_0000;
+    pub const EMAC_DES3_LD: u32 = 0x1000_0000;
+    pub const EMAC_DES3_ES: u32 = 0x0000_8000;
+    pub const EMAC_DES0_BUF1AP: u32 = 0xFFFF_FFFF;
+
+    pub const EMAC_TDES2_IOC: u32 = 0x8000_0000;
+    pub const EMAC_TDES2_B1L: u32 = 0x0000_3FFF;
+
+    pub const EMAC_RDES3_IOC: u32 = 0x4000_0000;
+    pub const EMAC_RDES3_PL: u32 = 0x0000_7FFF;
+    pub const EMAC_RDES3_BUF1V: u32 = 0x0100_0000;
+    pub const EMAC_RDES3_PKTLEN: u32 = 0x0000_7FFF;
+}
+use emac_consts::*;
+
+/// Transmit Descriptor representation
+///
+/// * tdes0: transmit buffer address
+/// * tdes1:
+/// * tdes2: buffer lengths
+/// * tdes3: control and payload/frame length
+#[repr(C)]
+struct TDes {
+    tdes0: VolatileCell<u32>,
+    tdes1: VolatileCell<u32>,
+    tdes2: VolatileCell<u32>,
+    tdes3: VolatileCell<u32>,
+}
+
+impl TDes {
+    pub const fn new() -> Self {
+        Self {
+            tdes0: VolatileCell::new(0),
+            tdes1: VolatileCell::new(0),
+            tdes2: VolatileCell::new(0),
+            tdes3: VolatileCell::new(0),
+        }
+    }
+
+    /// Return true if this TDes is not currently owned by the DMA
+    pub fn available(&self) -> bool {
+        self.tdes3.get() & EMAC_DES3_OWN == 0
+    }
+}
+
+pub(crate) struct TDesRing<const N: usize> {
+    td: [TDes; N],
+    buffers: [Option<PacketBuf>; N],
+    tdidx: usize,
+}
+
+impl<const N: usize> TDesRing<N> {
+    pub const fn new() -> Self {
+        const TDES: TDes = TDes::new();
+        const BUFFERS: Option<PacketBuf> = None;
+
+        Self {
+            td: [TDES; N],
+            buffers: [BUFFERS; N],
+            tdidx: 0,
+        }
+    }
+
+    /// Initialise this TDesRing. Assume TDesRing is corrupt
+    ///
+    /// The current memory address of the buffers inside this TDesRing
+    /// will be stored in the descriptors, so ensure the TDesRing is
+    /// not moved after initialisation.
+    pub(crate) fn init(&mut self) {
+        assert!(N > 0);
+
+        for td in self.td.iter_mut() {
+            *td = TDes::new();
+        }
+        self.tdidx = 0;
+
+        // Initialize the pointers in the DMA engine. (There will be a memory barrier later
+        // before the DMA engine is enabled.)
+        // NOTE (unsafe) Used for atomic writes
+        unsafe {
+            let dma = ETH.ethernet_dma();
+
+            dma.dmactx_dlar()
+                .write(|w| w.set_tdesla(&self.td as *const _ as u32));
+            dma.dmactx_rlr().write(|w| w.set_tdrl((N as u16) - 1));
+            dma.dmactx_dtpr()
+                .write(|w| w.set_tdt(&self.td[0] as *const _ as u32));
+        }
+    }
+
+    /// Return true if a TDes is available for use
+    pub(crate) fn available(&self) -> bool {
+        self.td[self.tdidx].available()
+    }
+
+    pub(crate) fn transmit(&mut self, pkt: PacketBuf) -> Result<(), Error> {
+        if !self.available() {
+            return Err(Error::NoBufferAvailable);
+        }
+        let x = self.tdidx;
+        let td = &mut self.td[x];
+
+        let pkt_len = pkt.len();
+        assert!(pkt_len as u32 <= EMAC_TDES2_B1L);
+        let address = pkt.as_ptr() as u32;
+
+        // Read format
+        td.tdes0.set(address);
+        td.tdes2
+            .set(pkt_len as u32 & EMAC_TDES2_B1L | EMAC_TDES2_IOC);
+
+        // FD: Contains first buffer of packet
+        // LD: Contains last buffer of packet
+        // Give the DMA engine ownership
+        td.tdes3.set(EMAC_DES3_FD | EMAC_DES3_LD | EMAC_DES3_OWN);
+
+        self.buffers[x].replace(pkt);
+
+        // Ensure changes to the descriptor are committed before DMA engine sees tail pointer store.
+        // This will generate an DMB instruction.
+        // "Preceding reads and writes cannot be moved past subsequent writes."
+        fence(Ordering::Release);
+
+        // Move the tail pointer (TPR) to the next descriptor
+        let x = (x + 1) % N;
+        // NOTE(unsafe) Atomic write
+        unsafe {
+            ETH.ethernet_dma()
+                .dmactx_dtpr()
+                .write(|w| w.set_tdt(&self.td[x] as *const _ as u32));
+        }
+        self.tdidx = x;
+        Ok(())
+    }
+
+    pub(crate) fn on_interrupt(&mut self) -> Result<(), Error> {
+        let previous = (self.tdidx + N - 1) % N;
+        let td = &self.td[previous];
+
+        // DMB to ensure that we are reading an updated value, probably not needed at the hardware
+        // level, but this is also a hint to the compiler that we're syncing on the buffer.
+        fence(Ordering::SeqCst);
+
+        let tdes3 = td.tdes3.get();
+
+        if tdes3 & EMAC_DES3_OWN != 0 {
+            // Transmission isn't done yet, probably a receive interrupt that fired this
+            return Ok(());
+        }
+        assert!(tdes3 & EMAC_DES3_CTXT == 0);
+
+        // Release the buffer
+        self.buffers[previous].take();
+
+        if tdes3 & EMAC_DES3_ES != 0 {
+            Err(Error::TransmissionError)
+        } else {
+            Ok(())
+        }
+    }
+}
+
+/// Receive Descriptor representation
+///
+/// * rdes0: recieve buffer address
+/// * rdes1:
+/// * rdes2:
+/// * rdes3: OWN and Status
+#[repr(C)]
+struct RDes {
+    rdes0: VolatileCell<u32>,
+    rdes1: VolatileCell<u32>,
+    rdes2: VolatileCell<u32>,
+    rdes3: VolatileCell<u32>,
+}
+
+impl RDes {
+    pub const fn new() -> Self {
+        Self {
+            rdes0: VolatileCell::new(0),
+            rdes1: VolatileCell::new(0),
+            rdes2: VolatileCell::new(0),
+            rdes3: VolatileCell::new(0),
+        }
+    }
+
+    /// Return true if this RDes is acceptable to us
+    #[inline(always)]
+    pub fn valid(&self) -> bool {
+        // Write-back descriptor is valid if:
+        //
+        // Contains first buffer of packet AND contains last buf of
+        // packet AND no errors AND not a context descriptor
+        self.rdes3.get() & (EMAC_DES3_FD | EMAC_DES3_LD | EMAC_DES3_ES | EMAC_DES3_CTXT)
+            == (EMAC_DES3_FD | EMAC_DES3_LD)
+    }
+
+    /// Return true if this RDes is not currently owned by the DMA
+    #[inline(always)]
+    pub fn available(&self) -> bool {
+        self.rdes3.get() & EMAC_DES3_OWN == 0 // Owned by us
+    }
+
+    #[inline(always)]
+    pub fn set_ready(&mut self, buf_addr: u32) {
+        self.rdes0.set(buf_addr);
+        self.rdes3
+            .set(EMAC_RDES3_BUF1V | EMAC_RDES3_IOC | EMAC_DES3_OWN);
+    }
+}
+
+pub(crate) struct RDesRing<const N: usize> {
+    rd: [RDes; N],
+    buffers: [Option<PacketBox>; N],
+    read_idx: usize,
+    tail_idx: usize,
+}
+
+impl<const N: usize> RDesRing<N> {
+    pub const fn new() -> Self {
+        const RDES: RDes = RDes::new();
+        const BUFFERS: Option<PacketBox> = None;
+
+        Self {
+            rd: [RDES; N],
+            buffers: [BUFFERS; N],
+            read_idx: 0,
+            tail_idx: 0,
+        }
+    }
+
+    pub(crate) fn init(&mut self) {
+        assert!(N > 1);
+
+        for desc in self.rd.iter_mut() {
+            *desc = RDes::new();
+        }
+
+        let mut last_index = 0;
+        for (index, buf) in self.buffers.iter_mut().enumerate() {
+            let pkt = match PacketBox::new(Packet::new()) {
+                Some(p) => p,
+                None => {
+                    if index == 0 {
+                        panic!("Could not allocate at least one buffer for Ethernet receiving");
+                    } else {
+                        break;
+                    }
+                }
+            };
+            let addr = pkt.as_ptr() as u32;
+            *buf = Some(pkt);
+            self.rd[index].set_ready(addr);
+            last_index = index;
+        }
+        self.tail_idx = (last_index + 1) % N;
+
+        unsafe {
+            let dma = ETH.ethernet_dma();
+
+            dma.dmacrx_dlar()
+                .write(|w| w.set_rdesla(self.rd.as_ptr() as u32));
+            dma.dmacrx_rlr().write(|w| w.set_rdrl((N as u16) - 1));
+
+            // We manage to allocate all buffers, set the index to the last one, that means
+            // that the DMA won't consider the last one as ready, because it (unfortunately)
+            // stops at the tail ptr and wraps at the end of the ring, which means that we
+            // can't tell it to stop after the last buffer.
+            let tail_ptr = &self.rd[last_index] as *const _ as u32;
+            fence(Ordering::Release);
+
+            dma.dmacrx_dtpr().write(|w| w.set_rdt(tail_ptr));
+        }
+    }
+
+    pub(crate) fn on_interrupt(&mut self) {
+        // TODO!
+    }
+
+    pub(crate) fn pop_packet(&mut self) -> Option<PacketBuf> {
+        // Not sure if the contents of the write buffer on the M7 can affects reads, so we are using
+        // a DMB here just in case, it also serves as a hint to the compiler that we're syncing the
+        // buffer (I think .-.)
+        fence(Ordering::SeqCst);
+
+        let read_available = self.rd[self.read_idx].available();
+        if !read_available && self.read_idx == self.tail_idx {
+            // Nothing to do
+            return None;
+        }
+
+        let pkt = if read_available {
+            let pkt = self.buffers[self.read_idx].take();
+            let len = (self.rd[self.read_idx].rdes3.get() & EMAC_RDES3_PKTLEN) as usize;
+
+            assert!(pkt.is_some());
+            let valid = self.rd[self.read_idx].valid();
+
+            self.read_idx = (self.read_idx + 1) % N;
+            if valid {
+                pkt.map(|p| p.slice(0..len))
+            } else {
+                None
+            }
+        } else {
+            None
+        };
+
+        match PacketBox::new(Packet::new()) {
+            Some(b) => {
+                let addr = b.as_ptr() as u32;
+                self.buffers[self.tail_idx].replace(b);
+                self.rd[self.tail_idx].set_ready(addr);
+
+                // "Preceding reads and writes cannot be moved past subsequent writes."
+                fence(Ordering::Release);
+
+                // NOTE(unsafe) atomic write
+                unsafe {
+                    ETH.ethernet_dma()
+                        .dmacrx_dtpr()
+                        .write(|w| w.set_rdt(&self.rd[self.read_idx] as *const _ as u32));
+                }
+
+                self.tail_idx = (self.tail_idx + 1) % N;
+            }
+            None => {}
+        }
+        pkt
+    }
+}
+
+pub struct DescriptorRing<const T: usize, const R: usize> {
+    pub(crate) tx: TDesRing<T>,
+    pub(crate) rx: RDesRing<R>,
+}
+
+impl<const T: usize, const R: usize> DescriptorRing<T, R> {
+    pub const fn new() -> Self {
+        Self {
+            tx: TDesRing::new(),
+            rx: RDesRing::new(),
+        }
+    }
+
+    pub fn init(&mut self) {
+        self.tx.init();
+        self.rx.init();
+    }
+}

embassy-stm32/src/eth/v2/mod.rs

@@ -0,0 +1,350 @@
+use core::marker::PhantomData;
+use core::pin::Pin;
+use core::sync::atomic::{fence, Ordering};
+
+use embassy::util::{AtomicWaker, Unborrow};
+use embassy_extras::peripheral::{PeripheralMutex, PeripheralState};
+use embassy_extras::unborrow;
+use embassy_net::MTU;
+
+use crate::gpio::sealed::Pin as __GpioPin;
+use crate::gpio::AnyPin;
+use crate::gpio::Pin as GpioPin;
+use crate::interrupt::Interrupt;
+use crate::pac::gpio::vals::Ospeedr;
+use crate::pac::ETH;
+use crate::peripherals;
+
+mod descriptors;
+use descriptors::DescriptorRing;
+
+/// Station Management Interface (SMI) on an ethernet PHY
+pub trait StationManagement {
+    /// Read a register over SMI.
+    fn smi_read(&mut self, reg: u8) -> u16;
+    /// Write a register over SMI.
+    fn smi_write(&mut self, reg: u8, val: u16);
+}
+
+/// Traits for an Ethernet PHY
+pub trait PHY {
+    /// Reset PHY and wait for it to come out of reset.
+    fn phy_reset(&mut self);
+    /// PHY initialisation.
+    fn phy_init(&mut self);
+}
+
+pub struct Ethernet<'d, T: Instance, const TX: usize, const RX: usize> {
+    state: PeripheralMutex<Inner<'d, T, TX, RX>>,
+    pins: [AnyPin; 9],
+}
+
+impl<'d, T: Instance, const TX: usize, const RX: usize> Ethernet<'d, T, TX, RX> {
+    pub fn new(
+        peri: impl Unborrow<Target = T> + 'd,
+        interrupt: impl Unborrow<Target = T::Interrupt> + 'd,
+        ref_clk: impl Unborrow<Target = impl RefClkPin<T>> + 'd,
+        mdio: impl Unborrow<Target = impl MDIOPin<T>> + 'd,
+        mdc: impl Unborrow<Target = impl MDCPin<T>> + 'd,
+        crs: impl Unborrow<Target = impl CRSPin<T>> + 'd,
+        rx_d0: impl Unborrow<Target = impl RXD0Pin<T>> + 'd,
+        rx_d1: impl Unborrow<Target = impl RXD1Pin<T>> + 'd,
+        tx_d0: impl Unborrow<Target = impl TXD0Pin<T>> + 'd,
+        tx_d1: impl Unborrow<Target = impl TXD1Pin<T>> + 'd,
+        tx_en: impl Unborrow<Target = impl TXEnPin<T>> + 'd,
+        mac_addr: [u8; 6],
+    ) -> Self {
+        unborrow!(interrupt, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
+
+        ref_clk.configure();
+        mdio.configure();
+        mdc.configure();
+        crs.configure();
+        rx_d0.configure();
+        rx_d1.configure();
+        tx_d0.configure();
+        tx_d1.configure();
+        tx_en.configure();
+
+        let inner = Inner::new(peri);
+        let state = PeripheralMutex::new(inner, interrupt);
+
+        // NOTE(unsafe) We have exclusive access to the registers
+        unsafe {
+            let dma = ETH.ethernet_dma();
+            let mac = ETH.ethernet_mac();
+            let mtl = ETH.ethernet_mtl();
+
+            // Reset and wait
+            dma.dmamr().modify(|w| w.set_swr(true));
+            while dma.dmamr().read().swr() {}
+
+            // 200 MHz ?
+            mac.mac1ustcr().modify(|w| w.set_tic_1us_cntr(200 - 1));
+
+            mac.maccr().modify(|w| {
+                w.set_ipg(0b000); // 96 bit times
+                w.set_acs(true);
+                w.set_fes(true);
+                w.set_dm(true);
+                // TODO: Carrier sense ? ECRSFD
+            });
+
+            mac.maca0lr().write(|w| {
+                w.set_addrlo(
+                    u32::from(mac_addr[0])
+                        | (u32::from(mac_addr[1]) << 8)
+                        | (u32::from(mac_addr[2]) << 16)
+                        | (u32::from(mac_addr[3]) << 24),
+                )
+            });
+            mac.maca0hr()
+                .modify(|w| w.set_addrhi(u16::from(mac_addr[4]) | (u16::from(mac_addr[5]) << 8)));
+
+            // TODO: Enable filtering once we get the basics working
+            mac.macpfr().modify(|w| w.set_ra(true));
+            mac.macqtx_fcr().modify(|w| w.set_pt(0x100));
+
+            mtl.mtlrx_qomr().modify(|w| w.set_rsf(true));
+            mtl.mtltx_qomr().modify(|w| w.set_tsf(true));
+
+            // TODO: Address aligned beats plus fixed burst ?
+            dma.dmactx_cr().modify(|w| w.set_txpbl(1)); // 32 ?
+            dma.dmacrx_cr().modify(|w| {
+                w.set_rxpbl(1); // 32 ?
+                w.set_rbsz(MTU as u16);
+            });
+        }
+
+        let pins = [
+            ref_clk.degrade(),
+            mdio.degrade(),
+            mdc.degrade(),
+            crs.degrade(),
+            rx_d0.degrade(),
+            rx_d1.degrade(),
+            tx_d0.degrade(),
+            tx_d1.degrade(),
+            tx_en.degrade(),
+        ];
+
+        Self { state, pins }
+    }
+
+    pub fn init(self: Pin<&mut Self>) {
+        // NOTE(unsafe) We won't move this
+        let this = unsafe { self.get_unchecked_mut() };
+        let mutex = unsafe { Pin::new_unchecked(&mut this.state) };
+
+        mutex.with(|s, _| {
+            s.desc_ring.init();
+
+            fence(Ordering::SeqCst);
+
+            unsafe {
+                let mac = ETH.ethernet_mac();
+                let mtl = ETH.ethernet_mtl();
+                let dma = ETH.ethernet_dma();
+
+                mac.maccr().modify(|w| {
+                    w.set_re(true);
+                    w.set_te(true);
+                });
+                mtl.mtltx_qomr().modify(|w| w.set_ftq(true));
+
+                dma.dmactx_cr().modify(|w| w.set_st(true));
+                dma.dmacrx_cr().modify(|w| w.set_sr(true));
+
+                // Enable interrupts
+                dma.dmacier().modify(|w| {
+                    w.set_nie(true);
+                    w.set_rie(true);
+                    w.set_tie(true);
+                });
+            }
+        });
+    }
+}
+
+impl<'d, T: Instance, const TX: usize, const RX: usize> Drop for Ethernet<'d, T, TX, RX> {
+    fn drop(&mut self) {
+        for pin in self.pins.iter_mut() {
+            // NOTE(unsafe) Exclusive access to the regs
+            critical_section::with(|_| unsafe {
+                pin.set_as_analog();
+                pin.block()
+                    .ospeedr()
+                    .modify(|w| w.set_ospeedr(pin.pin() as usize, Ospeedr::LOWSPEED));
+            })
+        }
+    }
+}
+
+//----------------------------------------------------------------------
+
+struct Inner<'d, T: Instance, const TX: usize, const RX: usize> {
+    _peri: PhantomData<&'d mut T>,
+    desc_ring: DescriptorRing<TX, RX>,
+}
+
+impl<'d, T: Instance, const TX: usize, const RX: usize> Inner<'d, T, TX, RX> {
+    pub fn new(_peri: impl Unborrow<Target = T> + 'd) -> Self {
+        Self {
+            _peri: PhantomData,
+            desc_ring: DescriptorRing::new(),
+        }
+    }
+}
+
+impl<'d, T: Instance, const TX: usize, const RX: usize> PeripheralState for Inner<'d, T, TX, RX> {
+    type Interrupt = T::Interrupt;
+
+    fn on_interrupt(&mut self) {
+        unwrap!(self.desc_ring.tx.on_interrupt());
+        self.desc_ring.rx.on_interrupt();
+
+        T::state().wake();
+
+        // TODO: Check and clear more flags
+        unsafe {
+            let dma = ETH.ethernet_dma();
+
+            dma.dmacsr().modify(|w| {
+                w.set_ti(false);
+                w.set_ri(false);
+            });
+            // Delay two peripheral's clock
+            dma.dmacsr().read();
+            dma.dmacsr().read();
+        }
+    }
+}
+
+mod sealed {
+    use super::*;
+
+    pub trait Instance {
+        type Interrupt: Interrupt;
+
+        fn state() -> &'static AtomicWaker;
+    }
+
+    pub trait RefClkPin<T: Instance>: GpioPin {
+        fn configure(&mut self);
+    }
+
+    pub trait MDIOPin<T: Instance>: GpioPin {
+        fn configure(&mut self);
+    }
+
+    pub trait MDCPin<T: Instance>: GpioPin {
+        fn configure(&mut self);
+    }
+
+    pub trait CRSPin<T: Instance>: GpioPin {
+        fn configure(&mut self);
+    }
+
+    pub trait RXD0Pin<T: Instance>: GpioPin {
+        fn configure(&mut self);
+    }
+
+    pub trait RXD1Pin<T: Instance>: GpioPin {
+        fn configure(&mut self);
+    }
+
+    pub trait TXD0Pin<T: Instance>: GpioPin {
+        fn configure(&mut self);
+    }
+
+    pub trait TXD1Pin<T: Instance>: GpioPin {
+        fn configure(&mut self);
+    }
+
+    pub trait TXEnPin<T: Instance>: GpioPin {
+        fn configure(&mut self);
+    }
+}
+
+pub trait Instance: sealed::Instance + 'static {}
+
+pub trait RefClkPin<T: Instance>: sealed::RefClkPin<T> + 'static {}
+
+pub trait MDIOPin<T: Instance>: sealed::MDIOPin<T> + 'static {}
+
+pub trait MDCPin<T: Instance>: sealed::MDCPin<T> + 'static {}
+
+pub trait CRSPin<T: Instance>: sealed::CRSPin<T> + 'static {}
+
+pub trait RXD0Pin<T: Instance>: sealed::RXD0Pin<T> + 'static {}
+
+pub trait RXD1Pin<T: Instance>: sealed::RXD1Pin<T> + 'static {}
+
+pub trait TXD0Pin<T: Instance>: sealed::TXD0Pin<T> + 'static {}
+
+pub trait TXD1Pin<T: Instance>: sealed::TXD1Pin<T> + 'static {}
+
+pub trait TXEnPin<T: Instance>: sealed::TXEnPin<T> + 'static {}
+
+crate::pac::peripherals!(
+    (eth, $inst:ident) => {
+        impl sealed::Instance for peripherals::$inst {
+            type Interrupt = crate::interrupt::$inst;
+
+            fn state() -> &'static AtomicWaker {
+                static WAKER: AtomicWaker = AtomicWaker::new();
+                &WAKER
+            }
+        }
+
+        impl Instance for peripherals::$inst {}
+    };
+);
+
+macro_rules! impl_pin {
+    ($inst:ident, $pin:ident, $signal:ident, $af:expr) => {
+        impl sealed::$signal<peripherals::$inst> for peripherals::$pin {
+            fn configure(&mut self) {
+                // NOTE(unsafe) Exclusive access to the registers
+                critical_section::with(|_| unsafe {
+                    self.set_as_af($af);
+                    self.block()
+                        .ospeedr()
+                        .modify(|w| w.set_ospeedr(self.pin() as usize, Ospeedr::VERYHIGHSPEED));
+                })
+            }
+        }
+
+        impl $signal<peripherals::$inst> for peripherals::$pin {}
+    };
+}
+
+crate::pac::peripheral_pins!(
+    ($inst:ident, eth, ETH, $pin:ident, REF_CLK, $af:expr) =>  {
+        impl_pin!($inst, $pin, RefClkPin, $af);
+    };
+    ($inst:ident, eth, ETH, $pin:ident, MDIO, $af:expr) =>  {
+        impl_pin!($inst, $pin, MDIOPin, $af);
+    };
+    ($inst:ident, eth, ETH, $pin:ident, MDC, $af:expr) =>  {
+        impl_pin!($inst, $pin, MDCPin, $af);
+    };
+    ($inst:ident, eth, ETH, $pin:ident, CRS_DV, $af:expr) =>  {
+        impl_pin!($inst, $pin, CRSPin, $af);
+    };
+    ($inst:ident, eth, ETH, $pin:ident, RXD0, $af:expr) =>  {
+        impl_pin!($inst, $pin, RXD0Pin, $af);
+    };
+    ($inst:ident, eth, ETH, $pin:ident, RXD1, $af:expr) =>  {
+        impl_pin!($inst, $pin, RXD1Pin, $af);
+    };
+    ($inst:ident, eth, ETH, $pin:ident, TXD0, $af:expr) =>  {
+        impl_pin!($inst, $pin, TXD0Pin, $af);
+    };
+    ($inst:ident, eth, ETH, $pin:ident, TXD1, $af:expr) =>  {
+        impl_pin!($inst, $pin, TXD1Pin, $af);
+    };
+    ($inst:ident, eth, ETH, $pin:ident, TX_EN, $af:expr) =>  {
+        impl_pin!($inst, $pin, TXEnPin, $af);
+    };
+);

embassy-stm32/src/lib.rs

@@ -29,6 +29,8 @@ pub mod clock;
 pub mod dac;
 #[cfg(dma)]
 pub mod dma;
+#[cfg(eth)]
+pub mod eth;
 #[cfg(i2c)]
 pub mod i2c;
 #[cfg(pwr)]