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Remove ad-hoc fixes for setting the IOSV bit to true

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This commit is contained in:
Emilie Burgun 2024-03-26 17:27:02 +01:00
parent ca998c170f
commit 402def86ee
3 changed files with 0 additions and 20 deletions
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7
embassy-stm32/src/gpio.rs
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@ -779,13 +779,6 @@ pub(crate) unsafe fn init(_cs: CriticalSection) {
<crate::peripherals::AFIO as crate::rcc::SealedRccPeripheral>::enable_and_reset_with_cs(_cs);
crate::_generated::init_gpio();
// Setting this bit is mandatory to use PG[15:2].
#[cfg(stm32u5)]
crate::pac::PWR.svmcr().modify(|w| {
w.set_io2sv(true);
w.set_io2vmen(true);
});
}
impl<'d> embedded_hal_02::digital::v2::InputPin for Input<'d> {

6
examples/stm32l4/src/bin/spe_adin1110_http_server.rs
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@ -93,12 +93,6 @@ async fn main(spawner: Spawner) {
let dp = embassy_stm32::init(config);
// RM0432rev9, 5.1.2: Independent I/O supply rail
// After reset, the I/Os supplied by VDDIO2 are logically and electrically isolated and
// therefore are not available. The isolation must be removed before using any I/O from
// PG[15:2], by setting the IOSV bit in the PWR_CR2 register, once the VDDIO2 supply is present
pac::PWR.cr2().modify(|w| w.set_iosv(true));
let reset_status = pac::RCC.bdcr().read().0;
defmt::println!("bdcr before: 0x{:X}", reset_status);

7
tests/stm32/src/common.rs
View File

@ -251,13 +251,6 @@ define_peris!(
);
pub fn config() -> Config {
// Setting this bit is mandatory to use PG[15:2].
#[cfg(feature = "stm32u5a5zj")]
embassy_stm32::pac::PWR.svmcr().modify(|w| {
w.set_io2sv(true);
w.set_io2vmen(true);
});
#[allow(unused_mut)]
let mut config = Config::default();