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rp: Fix indexing for pins >31 on rp235xb (#3330)
* Fix indexing for pins >31 on rp235xb * fixup knowing that 1<<7 is 128 not 64
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@ -846,12 +846,12 @@ pub(crate) trait SealedPin: Sized {
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#[inline]
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#[inline]
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fn _pin(&self) -> u8 {
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fn _pin(&self) -> u8 {
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self.pin_bank() & 0x1f
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self.pin_bank() & 0x7f
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}
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}
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#[inline]
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#[inline]
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fn _bank(&self) -> Bank {
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fn _bank(&self) -> Bank {
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match self.pin_bank() >> 5 {
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match self.pin_bank() >> 7 {
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#[cfg(feature = "qspi-as-gpio")]
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#[cfg(feature = "qspi-as-gpio")]
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1 => Bank::Qspi,
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1 => Bank::Qspi,
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_ => Bank::Bank0,
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_ => Bank::Bank0,
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@ -880,15 +880,27 @@ pub(crate) trait SealedPin: Sized {
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}
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}
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fn sio_out(&self) -> pac::sio::Gpio {
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fn sio_out(&self) -> pac::sio::Gpio {
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SIO.gpio_out(self._bank() as _)
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if cfg!(feature = "rp2040") {
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SIO.gpio_out(self._bank() as _)
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} else {
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SIO.gpio_out((self._pin() / 32) as _)
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}
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}
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}
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fn sio_oe(&self) -> pac::sio::Gpio {
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fn sio_oe(&self) -> pac::sio::Gpio {
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SIO.gpio_oe(self._bank() as _)
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if cfg!(feature = "rp2040") {
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SIO.gpio_oe(self._bank() as _)
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} else {
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SIO.gpio_oe((self._pin() / 32) as _)
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}
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}
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}
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fn sio_in(&self) -> Reg<u32, RW> {
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fn sio_in(&self) -> Reg<u32, RW> {
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SIO.gpio_in(self._bank() as _)
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if cfg!(feature = "rp2040") {
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SIO.gpio_in(self._bank() as _)
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} else {
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SIO.gpio_in((self._pin() / 32) as _)
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}
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}
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}
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fn int_proc(&self) -> pac::io::Int {
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fn int_proc(&self) -> pac::io::Int {
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@ -953,7 +965,7 @@ macro_rules! impl_pin {
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impl SealedPin for peripherals::$name {
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impl SealedPin for peripherals::$name {
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#[inline]
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#[inline]
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fn pin_bank(&self) -> u8 {
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fn pin_bank(&self) -> u8 {
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($bank as u8) * 32 + $pin_num
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($bank as u8) * 128 + $pin_num
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}
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}
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}
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}
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