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fix g0 being left out of some clock controls

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This commit is contained in:
Adin Ackerman 2024-01-02 16:03:23 -08:00
parent a769ac188f
commit 34713b4910
3 changed files with 30 additions and 11 deletions
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2
embassy-stm32/build.rs
View File

@ -505,7 +505,7 @@ fn main() {
(TokenStream::new(), TokenStream::new())
};
let mux_supported = HashSet::from(["c0", "h5", "h50", "h7", "h7ab", "h7rm0433", "g4", "l4"])
let mux_supported = HashSet::from(["c0", "h5", "h50", "h7", "h7ab", "h7rm0433", "g0", "g4", "l4"])
.contains(rcc_registers.version);
let mux_for = |mux: Option<&'static PeripheralRccRegister>| {
// restrict mux implementation to supported versions

27
embassy-stm32/src/rcc/g0.rs
View File

@ -95,7 +95,7 @@ impl Default for Config {
}
impl PllConfig {
pub(crate) fn init(self) -> Hertz {
pub(crate) fn init(self) -> (Hertz, Option<Hertz>, Option<Hertz>) {
let (src, input_freq) = match self.source {
PllSource::HSI => (vals::Pllsrc::HSI, HSI_FREQ),
PllSource::HSE(freq, _) => (vals::Pllsrc::HSE, freq),
@ -118,6 +118,9 @@ impl PllConfig {
// > Caution: The software must set this bitfield so as not to exceed 64 MHz on this clock.
debug_assert!(r_freq.0 <= 64_000_000);
let q_freq = self.q.map(|q| n_freq / q);
let p_freq = self.p.map(|p| n_freq / p);
// RM0454 § 5.2.3:
// > To modify the PLL configuration, proceed as follows:
// > 1. Disable the PLL by setting PLLON to 0 in Clock control register (RCC_CR).
@ -172,11 +175,14 @@ impl PllConfig {
w.set_pllpen(self.p.is_some());
});
r_freq
(r_freq, q_freq, p_freq)
}
}
pub(crate) unsafe fn init(config: Config) {
let mut pll1_q_freq = None;
let mut pll1_p_freq = None;
let (sys_clk, sw) = match config.mux {
ClockSrc::HSI(div) => {
// Enable HSI
@ -199,8 +205,12 @@ pub(crate) unsafe fn init(config: Config) {
(freq, Sw::HSE)
}
ClockSrc::PLL(pll) => {
let freq = pll.init();
(freq, Sw::PLL1_R)
let (r_freq, q_freq, p_freq) = pll.init();
pll1_q_freq = q_freq;
pll1_p_freq = p_freq;
(r_freq, Sw::PLL1_R)
}
ClockSrc::LSI => {
// Enable LSI
@ -286,12 +296,21 @@ pub(crate) unsafe fn init(config: Config) {
}
let rtc = config.ls.init();
let lse_freq = config.ls.lse.map(|lse| lse.frequency);
let hsi_freq = (sw == Sw::HSI).then_some(HSI_FREQ);
let lsi_freq = (sw == Sw::LSI).then_some(super::LSI_FREQ);
set_freqs(Clocks {
sys: sys_clk,
hclk1: ahb_freq,
pclk1: apb_freq,
pclk1_tim: apb_tim_freq,
hsi: hsi_freq,
lse: lse_freq,
lsi: lsi_freq,
pll1_q: pll1_q_freq,
pll1_p: pll1_p_freq,
rtc,
});
}

10
embassy-stm32/src/rcc/mod.rs
View File

@ -121,9 +121,9 @@ pub struct Clocks {
#[cfg(rcc_l4)]
pub pllsai2_p: Option<Hertz>,
#[cfg(any(stm32g4, rcc_l4))]
#[cfg(any(stm32g0, stm32g4, rcc_l4))]
pub pll1_p: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7, stm32f2, stm32f4, stm32f7, rcc_l4, stm32g4))]
#[cfg(any(stm32h5, stm32h7, stm32f2, stm32f4, stm32f7, rcc_l4, stm32g0, stm32g4))]
pub pll1_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_p: Option<Hertz>,
@ -160,16 +160,16 @@ pub struct Clocks {
pub rtc: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0))]
#[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0, stm32g0))]
pub hsi: Option<Hertz>,
#[cfg(stm32h5)]
pub hsi48: Option<Hertz>,
#[cfg(stm32h5)]
#[cfg(any(stm32g0, stm32h5))]
pub lsi: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub csi: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0))]
#[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0, stm32g0))]
pub lse: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7, stm32g4))]
pub hse: Option<Hertz>,