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Update STM32 RCC U5 to support P and Q dividers

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This commit is contained in:
Tyler Gilbert 2024-01-03 10:46:45 -06:00
parent 3b6eaf414a
commit 31bf127807
2 changed files with 20 additions and 0 deletions
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18
embassy-stm32/src/rcc/u5.rs
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@ -45,6 +45,18 @@ pub struct PllConfig {
/// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544
/// MHz. The upper limit may be lower depending on the `Config { voltage_range }`.
pub n: Plln,
/// The divider for the P output.
///
/// When used to drive the system clock, `source` divided by `m` times `n` divided by `r`
/// must not exceed 160 MHz. System clocks above 55 MHz require a non-default
/// `Config { voltage_range }`.
pub p: Plldiv,
/// The divider for the Q output.
///
/// When used to drive the system clock, `source` divided by `m` times `n` divided by `r`
/// must not exceed 160 MHz. System clocks above 55 MHz require a non-default
/// `Config { voltage_range }`.
pub q: Plldiv,
/// The divider for the R output.
///
/// When used to drive the system clock, `source` divided by `m` times `n` divided by `r`
@ -60,6 +72,8 @@ impl PllConfig {
source: PllSource::HSI,
m: Pllm::DIV1,
n: Plln::MUL10,
p: Plldiv::DIV3,
q: Plldiv::DIV2,
r: Plldiv::DIV1,
}
}
@ -70,6 +84,8 @@ impl PllConfig {
source: PllSource::MSIS(Msirange::RANGE_48MHZ),
m: Pllm::DIV3,
n: Plln::MUL10,
p: Plldiv::DIV3,
q: Plldiv::DIV2,
r: Plldiv::DIV1,
}
}
@ -301,6 +317,8 @@ pub(crate) unsafe fn init(config: Config) {
RCC.pll1divr().modify(|w| {
// Set the VCO multiplier
w.set_plln(pll.n);
w.set_pllp(pll.p);
w.set_pllq(pll.q);
// Set the R output divisor
w.set_pllr(pll.r);
});

2
examples/stm32u5/src/bin/usb_serial.rs
View File

@ -26,6 +26,8 @@ async fn main(_spawner: Spawner) {
source: PllSource::HSI,
m: Pllm::DIV2,
n: Plln::MUL10,
p: Plldiv::DIV1,
q: Plldiv::DIV1,
r: Plldiv::DIV1,
});
config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true }); // needed for USB