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Merge pull request #3188 from ninjasource/sdmmc-dma-buffers
embassy-stm32: Allow cmd block to be passed in for sdmmc dma transfers
This commit is contained in:
commit
2537fc6f4f
@ -94,6 +94,34 @@ impl DerefMut for DataBlock {
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}
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}
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/// Command Block buffer for SDMMC command transfers.
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///
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/// This is a 16-word array, exposed so that DMA commpatible memory can be used if required.
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#[derive(Debug, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct CmdBlock(pub [u32; 16]);
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impl CmdBlock {
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/// Creates a new instance of CmdBlock
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pub const fn new() -> Self {
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Self([0u32; 16])
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}
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}
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impl Deref for CmdBlock {
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type Target = [u32; 16];
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl DerefMut for CmdBlock {
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fn deref_mut(&mut self) -> &mut Self::Target {
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&mut self.0
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}
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}
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/// Errors
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#[non_exhaustive]
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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@ -292,6 +320,10 @@ pub struct Sdmmc<'d, T: Instance, Dma: SdmmcDma<T> = NoDma> {
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signalling: Signalling,
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/// Card
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card: Option<Card>,
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/// An optional buffer to be used for commands
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/// This should be used if there are special memory location requirements for dma
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cmd_block: Option<&'d mut CmdBlock>,
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}
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const CLK_AF: AfType = AfType::output(OutputType::PushPull, Speed::VeryHigh);
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@ -495,6 +527,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
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clock: SD_INIT_FREQ,
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signalling: Default::default(),
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card: None,
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cmd_block: None,
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}
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}
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@ -531,8 +564,10 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
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/// # Safety
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///
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/// `buffer` must be valid for the whole transfer and word aligned
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#[allow(unused_variables)]
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fn prepare_datapath_read<'a>(
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&'a mut self,
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config: &Config,
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dma: &'a mut PeripheralRef<'d, Dma>,
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buffer: &'a mut [u32],
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length_bytes: u32,
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block_size: u8,
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@ -544,15 +579,14 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
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Self::wait_idle();
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Self::clear_interrupt_flags();
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regs.dtimer()
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.write(|w| w.set_datatime(self.config.data_transfer_timeout));
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regs.dtimer().write(|w| w.set_datatime(config.data_transfer_timeout));
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regs.dlenr().write(|w| w.set_datalength(length_bytes));
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#[cfg(sdmmc_v1)]
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let transfer = unsafe {
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let request = self.dma.request();
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let request = dma.request();
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Transfer::new_read(
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&mut self.dma,
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dma,
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request,
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regs.fifor().as_ptr() as *mut u32,
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buffer,
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@ -692,13 +726,16 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
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Signalling::SDR12 => 0xFF_FF00,
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};
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let mut status = [0u32; 16];
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let status = match self.cmd_block.as_deref_mut() {
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Some(x) => x,
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None => &mut CmdBlock::new(),
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};
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// Arm `OnDrop` after the buffer, so it will be dropped first
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let regs = T::regs();
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let on_drop = OnDrop::new(|| Self::on_drop());
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let transfer = self.prepare_datapath_read(&mut status, 64, 6);
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let transfer = Self::prepare_datapath_read(&self.config, &mut self.dma, status.as_mut(), 64, 6);
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InterruptHandler::<T>::data_interrupts(true);
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Self::cmd(Cmd::cmd6(set_function), true)?; // CMD6
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@ -770,16 +807,21 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
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let card = self.card.as_mut().ok_or(Error::NoCard)?;
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let rca = card.rca;
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let cmd_block = match self.cmd_block.as_deref_mut() {
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Some(x) => x,
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None => &mut CmdBlock::new(),
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};
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Self::cmd(Cmd::set_block_length(64), false)?; // CMD16
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Self::cmd(Cmd::app_cmd(rca << 16), false)?; // APP
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let mut status = [0u32; 16];
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let status = cmd_block;
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// Arm `OnDrop` after the buffer, so it will be dropped first
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let regs = T::regs();
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let on_drop = OnDrop::new(|| Self::on_drop());
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let transfer = self.prepare_datapath_read(&mut status, 64, 6);
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let transfer = Self::prepare_datapath_read(&self.config, &mut self.dma, status.as_mut(), 64, 6);
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InterruptHandler::<T>::data_interrupts(true);
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Self::cmd(Cmd::card_status(0), true)?;
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@ -813,7 +855,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
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for byte in status.iter_mut() {
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*byte = u32::from_be(*byte);
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}
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self.card.as_mut().unwrap().status = status.into();
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self.card.as_mut().unwrap().status = status.0.into();
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}
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res
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}
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@ -872,13 +914,17 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
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Self::cmd(Cmd::set_block_length(8), false)?; // CMD16
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Self::cmd(Cmd::app_cmd(card.rca << 16), false)?;
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let mut scr = [0u32; 2];
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let cmd_block = match self.cmd_block.as_deref_mut() {
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Some(x) => x,
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None => &mut CmdBlock::new(),
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};
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let scr = &mut cmd_block.0[..2];
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// Arm `OnDrop` after the buffer, so it will be dropped first
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let regs = T::regs();
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let on_drop = OnDrop::new(|| Self::on_drop());
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let transfer = self.prepare_datapath_read(&mut scr[..], 8, 3);
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let transfer = Self::prepare_datapath_read(&self.config, &mut self.dma, scr, 8, 3);
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InterruptHandler::<T>::data_interrupts(true);
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Self::cmd(Cmd::cmd51(), true)?;
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@ -910,7 +956,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
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drop(transfer);
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unsafe {
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let scr_bytes = &*(&scr as *const [u32; 2] as *const [u8; 8]);
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let scr_bytes = &*(&scr as *const _ as *const [u8; 8]);
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card.scr = SCR(u64::from_be_bytes(*scr_bytes));
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}
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}
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@ -1002,8 +1048,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
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Self::stop_datapath();
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}
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/// Initializes card (if present) and sets the bus at the
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/// specified frequency.
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/// Initializes card (if present) and sets the bus at the specified frequency.
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pub async fn init_card(&mut self, freq: Hertz) -> Result<(), Error> {
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let regs = T::regs();
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let ker_ck = T::frequency();
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@ -1143,6 +1188,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
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}
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}
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}
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// Read status after signalling change
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self.read_sd_status().await?;
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@ -1168,7 +1214,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
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let regs = T::regs();
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let on_drop = OnDrop::new(|| Self::on_drop());
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let transfer = self.prepare_datapath_read(buffer, 512, 9);
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let transfer = Self::prepare_datapath_read(&self.config, &mut self.dma, buffer, 512, 9);
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InterruptHandler::<T>::data_interrupts(true);
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Self::cmd(Cmd::read_single_block(address), true)?;
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@ -1291,6 +1337,14 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
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pub fn clock(&self) -> Hertz {
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self.clock
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}
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/// Set a specific cmd buffer rather than using the default stack allocated one.
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/// This is required if stack RAM cannot be used with DMA and usually manifests
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/// itself as an indefinite wait on a dma transfer because the dma peripheral
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/// cannot access the memory.
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pub fn set_cmd_block(&mut self, cmd_block: &'d mut CmdBlock) {
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self.cmd_block = Some(cmd_block)
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}
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}
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impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Drop for Sdmmc<'d, T, Dma> {
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