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bypass ODEN
if chip doesn't have it
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parent
88b2cdd6a0
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@ -2,7 +2,7 @@ pub use crate::pac::rcc::vals::{
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Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp, Pllq, Pllr, Pllsrc as PllSource,
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Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp, Pllq, Pllr, Pllsrc as PllSource,
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Ppre as APBPrescaler, Sw as Sysclk,
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Ppre as APBPrescaler, Sw as Sysclk,
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};
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};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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use crate::time::Hertz;
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@ -101,11 +101,17 @@ impl Default for Config {
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pub(crate) unsafe fn init(config: Config) {
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pub(crate) unsafe fn init(config: Config) {
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// always enable overdrive for now. Make it configurable in the future.
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// always enable overdrive for now. Make it configurable in the future.
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PWR.cr1().modify(|w| w.set_oden(true));
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#[cfg(not(any(
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while !PWR.csr1().read().odrdy() {}
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stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f405, stm32f407, stm32f415, stm32f417
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)))]
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{
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use crate::pac::PWR;
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PWR.cr1().modify(|w| w.set_oden(true));
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while !PWR.csr1().read().odrdy() {}
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PWR.cr1().modify(|w| w.set_odswen(true));
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PWR.cr1().modify(|w| w.set_odswen(true));
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while !PWR.csr1().read().odswrdy() {}
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while !PWR.csr1().read().odswrdy() {}
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}
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// Configure HSI
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// Configure HSI
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let hsi = match config.hsi {
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let hsi = match config.hsi {
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